公开(公告)号：JPH0519869B2

公开(公告)日：1993-03-17

申请号：JP18093584

申请日：1984-08-30

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  HAYASHI JUJI

IPC: H04N5/66 ,  G09F9/35 ,  G09G3/36 ,  H04N9/12

公开(公告)号：JPH0245372B2

公开(公告)日：1990-10-09

申请号：JP7808880

申请日：1980-06-10

Applicant: SONY CORP

Inventor： TSUCHA TAKAHISA ,  SONEDA MITSUO

IPC: H01L29/78 ,  G11C19/18 ,  G11C27/04 ,  H03H11/26 ,  H03H15/02 ,  H04N5/30

公开(公告)号：JPS63146515A

公开(公告)日：1988-06-18

申请号：JP29327686

申请日：1986-12-09

Applicant: SONY CORP

Inventor： SONEDA MITSUO

IPC: H03M1/66

Abstract: PURPOSE:To obtain an always excellent analog conversion output by forming an interpolation filter in one and same IC and changing the frequency characteristic of the filter in response to the frequency of the sampling clock. CONSTITUTION:A DA conversion section 1 and a filter 10 whose frequency characteristic is changed by a clock signal are formed in one and sane IC 20 and the filter is controlled by a clock signal having a frequency relating to (multiplier circuit 13) a sampling clock (at terminal 12) of the DA conversion section l in the titled DA conversion circuit. Thus, since the band characteristic of a low pass filter is changed in response to the clock signal, the circuit is realized with simple constitution.

公开(公告)号：JPS6396800A

公开(公告)日：1988-04-27

申请号：JP24223786

申请日：1986-10-13

Applicant: SONY CORP

Inventor： SONEDA MITSUO

IPC: G11C27/02

Abstract: PURPOSE:To eliminate off-set between input/output voltages and to prevent a potential from fluctuating in a holding period by providing plural switches which are turned on independently during a sampling and the holding, and isolating a current source and a level shift circuit from a charge/discharge capacitor and a CMOS inverter during the sampling. CONSTITUTION:The voltages of gates S3 and S1 are the same as those of gates S4 and S2. Where a voltage between points A and B is DELTAv, a voltage VOUT at the point B is equalized to VIN+DELTAv during the sampling when the gates S1-S3 and S5 are turned on and the gate S4 is turned off. The holding period is observed when the gates S1-S3 and S5 are turned off and the gate S4 is turned on. The current source and the level shift circuit including MOS transistors M3 and M4 are interrupted from the CMOS inverter circuit including MOS transistors M1 and M2. Thus even if the current I0 and I0' of the current source are not completely the same, or the MOS transistors M3 and M4 are slightly different, a potential at the point B is hardly fluctuated during the holding.

公开(公告)号：JPS6384204A

公开(公告)日：1988-04-14

申请号：JP22874586

申请日：1986-09-27

Applicant: SONY CORP

Inventor： SONEDA MITSUO

IPC: H03K3/03

Abstract: PURPOSE:To obtain a prescribed stable voltage by connecting odd number of stages of inverters in a ring and providing a loop connecting a couple of nodes interposed with an even number stage of inverters and providing an impedance conversion means controlling then by a voltage. CONSTITUTION:An odd number stage of inverters In1... are connected in series and an output of the final stage In3N is inputted to a 1st stage In1 to form a ring. The inverters In1, In2 are provided with a 1st loop L1 and MOS TRs M1-MN are provided as the impedance conversion means to the loops L1-LN and a control voltage VCTL is fed to each gate. A current flowing to the loop is controlled by the voltage VCTL to vary an oscillation frequency f0. Since the output of the required oscillation frequency f0 does not fluctuate a power voltage VDD fed directly to the inverters, a prescribed output level is always maintained.

公开(公告)号：JPS6382184A

公开(公告)日：1988-04-12

申请号：JP22736386

申请日：1986-09-26

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  MATSUSHITA TAKESHI ,  NAKAMURA JUNPEI ,  MORI HIROSHI

IPC: H04N9/30 ,  H04N9/12

Abstract: PURPOSE:To improve the resolution of display and to reduce color arrangement noise by arranging green display picture elements in mosaic and arranging other colors alternately inbetween. CONSTITUTION:The green color display picture elements G are arranged in mosaic and the other color display picture elements R, B are arranged alternately inbetween to set the aperture rate of the green display picture elements to 1/2 of the aperture rate of the other color display picture elements. Since the green display picture elements are arranged in mosaic and the red and blue display picture elements are arranged alternately inbetween, then the display picture elements of the same color are not arranged in horizontal/vertical/ oblique directions and so-called color arrangement noise such as color stripe is not caused. Since the green display picture elements giving the largest effect onto the visual resolution are arranged in mosaic, the resolution of display is much improved.

公开(公告)号：JPS6379415A

公开(公告)日：1988-04-09

申请号：JP22455886

申请日：1986-09-22

Applicant: SONY CORP

Inventor： SONEDA MITSUO

IPC: H03K5/08 ,  H03K5/24 ,  H03M1/34

Abstract: PURPOSE:To prevent the occurrence of noise by switching a signal potential and a reference potential in opposite phase to each other, applying them to two sets of circuits driven inversely and applying positive feedback from one output terminal to the other input terminal. CONSTITUTION:The signal potential Vs and the reference potential Vr are fed to capacitors 6a, 6b via switches 4a, 4b switched in opposite phase. The other terminals of the capacitors 6a, 6b are connected to output terminals 10a, 10b via inverter amplifiers 7a, 7b. The input and output of the inverter amplifiers 7a, 7b are switched by intermittent switches 8a, 8b and the output of one inverter amplifier 7a(7b) is fed back positively to the input of the other inverter amplifier 7b(7a) via an intermittent switch 9b(9a). Thus, the output of one amplifier is stabilized to a high potential and the other is stabilized to a low potential, a high gain is obtained and the occurrence of noise is prevented.

公开(公告)号：JPS6353967A

公开(公告)日：1988-03-08

申请号：JP19695186

申请日：1986-08-22

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  HAYASHI HISAO

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H03G3/10

Abstract: PURPOSE:To carry out favorable gain control where DC potential fluctuations are stationary and a dynamic range does not show a decrease by forming a well region on a SOI substrate and forming gate regions on the well through an insulation layer and controlling an electric field between the well region and the gate regions. CONSTITUTION:A well 2 is formed on a substrate 1 and an insulator 3 is formed on the well 2 and then a MOS region including gates 7a-7b is formed on the insulator 3. Once a voltage between the well region 2 and gate regions 7a and 7b is controlled, a longitudinal electric field of each MOS transistor channel between the above well region and the gate regions varies and the mobility also varies to control gm of each MOS transistor. Thus a gain of output signals is controlled by controlling gm of each transistor.

公开(公告)号：JPS6337897A

公开(公告)日：1988-02-18

申请号：JP18040786

申请日：1986-07-31

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  HAZAMA YOSHIKAZU

IPC: G11C27/02

Abstract: PURPOSE:To attain sufficient correction even with a large capacitance by providing a capacitor between a holding means and a buffer circuit, charging an offset voltage of a buffer into the capacitor during the sampling extraction period and obtaining a remaining output signal voltage during a holding period. CONSTITUTION:An input at a terminal 1 is performed during a sampling period phis by turning on a switch SW2, a voltage Vin is held in a capacitor C3, the Vin is given to a gate of a FET 8 by turning on SWs 12-15 and turning off SWs 4, 6 during the same period phi's to turn on the FET 8 and a voltage (Vin-VGS) is obtained by a source. By turning off the SWs 12-15, the voltage VGS is held in capacitors C5, C7 the SWs 4, 6 are turned on for a period phiH and the Vin in the C3 and the VGS in the C5 and C7 are added in series, and the result it fed to the gate. When the capacitances of the C5, C6 are denoted by C1, C2 respectively, then 2VGS is divided by 1/2 each with a prescribed input capacitor CA by turning on the SW 4, 6, a voltage Vin+VGS is applied to the gate and the Vin decreased by VGS is outputted at an output terminal 11. Through the constitution above, even with a large input capacitance CA, the VGS component is eliminated excellently, and even if the VGS is fluctuated, the DC potential fluctuation between the input and output is eliminated and excellent sample holding is applied.

公开(公告)号：JPS6329965A

公开(公告)日：1988-02-08

申请号：JP17433786

申请日：1986-07-24

Applicant: SONY CORP

Inventor： SONEDA MITSUO ,  HAYASHI HISAO

IPC: H01L21/8234 ,  H01L27/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE:To enable a delay amount of an output signal to be controlled without variation of output level, by applying variable voltage to a region located under a field effect transistor on the surface of a conductor. CONSTITUTION:An N-channel MOSFETMn constituting a CMOS inverter of a field effect semiconductor device is opposed, at the bottom side thereof, to a semiconductor well through an insulation film 3, and a delay control signal can be applied between the semiconductor well 2 and the ground. The delay control signal can control the amount of delay of the N-channel MOSFETMn and, hence, can change the delay time between input and output of the CMOS inverter constituted by the N-channel MOSFETMn. Therefore, a supply voltage Vdd applied to the MOS inverter need not be varied and the output signal level of the MOS will not vary.