公开(公告)号：EP0697723A2

公开(公告)日：1996-02-21

申请号：EP95480097.5

申请日：1995-07-24

Applicant: International Business Machines Corporation

Inventor： Cronin, John Edward ,  Thomas, David Charles ,  Buker, Edward Daniel ,  Anderson, Christine Ann ,  Kerszkowski, Gloria Jean

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76813 ,  H01L2221/1036

Abstract: A process for making metal features in an insulator layer in integrated circuits is disclosed. The process involves depositing an antireflective coating layer of a material such as TiN over the insulator layer patterning both the ARC and the insulator with a series of channels or apertures vias and depositing a metal such as tungsten over the ARC and in the channels and apertures. The metal can then be planarized by CMP using the insulator as an etch stop.

Abstract translation: 公开了一种用于在集成电路中的绝缘体层中制造金属特征的工艺。 该方法包括在绝缘体层上沉积诸如TiN的材料的抗反射涂层，所述绝缘体层通过一系列通道或孔通孔构图ARC和绝缘体，并且在ARC和通道和孔中沉积诸如钨的金属。 然后可以通过使用绝缘体作为蚀刻停止层的CMP来平坦化金属。 $$

公开(公告)号：EP0435187A2

公开(公告)日：1991-07-03

申请号：EP90125081.1

申请日：1990-12-21

Applicant: FUJITSU LIMITED

Inventor： Kobayashi, Koichi, c/o Fujitsu Limited

IPC: H01L21/28 ,  H01L21/314

CPC classification number: H01L21/76882 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76831 ,  H01L23/485 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2924/0002 ,  Y10S438/97 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor devices, comprising the steps of:-

(1) forming a plurality of insulating films (22, 23) on a base layer (21), said plurality of insulating films comprising at least a lower layer insulating film (22) and an upper layer insulating film (23), said lower layer insulating film being smaller in etch rate than said upper layer insulating film and serving as an etching stopper, and
forming a first opening portion (24) by etching said upper layer insulating film, and exposing said lower layer insulating film in said first opening portion, and
forming a second opening portion (25) smaller in width than said first opening portion by etching said lower layer insulating film, at a location beneath said first opening portion, and exposing said base layer in said second opening portion; then
(2) forming a metal layer (26) in said first and second opening portions so that it can contact with said base layer exposed in said second opening portion; then
(3) burying said metal layer in said first and second opening portions and planarising the buried metal layer by irradiating said metal layer with a laser beam (30).

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：（1）在基层（21）上形成多个绝缘膜（22,23），所述多个绝缘膜至少包括下层绝缘膜（ 所述下层绝缘膜的刻蚀速率小于所述上层绝缘膜并且用作刻蚀阻挡层，并且通过刻蚀所述上层绝缘膜形成第一开口部分（24） 在所述第一开口部分中暴露所述下层绝缘膜，并且通过在所述第一开口部分下面的位置蚀刻所述下层绝缘膜，形成宽度小于所述第一开口部分的第二开口部分（25）;以及 在所述第二开口部分中暴露所述基层; 然后（2）在所述第一和第二开口部分中形成金属层（26），使得它能够与暴露在所述第二开口部分中的所述基层接触; 然后（3）通过用激光束（30）照射所述金属层，将所述金属层掩埋在所述第一和第二开口部分中并平坦化所述埋入金属层。

公开(公告)号：EP3076430B1

公开(公告)日：2017-08-30

申请号：EP16168570.6

申请日：2003-02-14

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji

IPC: H01L23/58 ,  G03F1/26 ,  H01L21/768 ,  G03F1/32

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

公开(公告)号：EP2264758B1

公开(公告)日：2017-03-01

申请号：EP10177318.2

申请日：2002-12-05

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Shimizu, Noriyoshi ,  Suzuki, Takashi

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76811 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP3070740A1

公开(公告)日：2016-09-21

申请号：EP16168579.7

申请日：2003-02-14

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: H01L23/58 ,  H01L21/768

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: There is provided a semiconductor device, comprising a substrate (101) that includes an integrated circuit region (1), first and second interlayer insulation films (108, 111, 112) formed above the substrate, and a reinforcing structure comprising a main-wall part (2) and a sub-wall part (3) which are formed in the first and second interlayer insulation films, wherein the main-wall part surrounds the integrated circuit region in a periphery thereof and the sub-wall part is provided apart from the main-wall part in a corner region of the semiconductor device and is located between the integrated circuit region and the first bend section of the main-wall part. Both the main-wall part and the sub-wall part are formed by metal-filled trenches (131, 132) in the first and second interlayer insulation films.

公开(公告)号：EP2706410B1

公开(公告)日：2016-08-03

申请号：EP13195857.1

申请日：2003-02-14

Applicant: Fujitsu Semiconductor Limited

Inventor： Watanabe, Kenichi ,  Kawano, Michiari ,  Namba, Hiroshi ,  Sukegawa, Kazuo ,  Hasegawa, Takumi ,  Sawada, Toyoji ,  Mitani, Junichi

IPC: G03F1/26 ,  H01L23/00 ,  H01L23/58 ,  H01L21/768

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

公开(公告)号：EP1974379A2

公开(公告)日：2008-10-01

申请号：EP07710226.7

申请日：2007-01-19

Applicant: International Business Machines Corporation

Inventor： COOLBAUGH, Douglas D. ,  DOWNES, Keith E. ,  LINDGREN, Peter J. ,  STAMPER, Anthony K.

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via (26) is etched in a stacked structure and a border (32) is formed about the at least one partial via (26). The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer (22).

公开(公告)号：EP1120822A4

公开(公告)日：2004-11-10

申请号：EP99940607

申请日：1999-09-01

Applicant: TOKYO ELECTRON LTD

Inventor： AKAHORI TAKASHI ,  INAZAWA KOUICHIRO ,  SENOO KOUJI ,  HAGIWARA MASAAKI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/3127 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76835 ,  H01L2221/1031 ,  H01L2221/1036

Abstract: A semiconductor device using, e.g., a fluorine containing carbon film, as an interlayer dielectric film is produced by a dual damascene method which is a simple technique. After an dielectric film, e.g., an SiO2 film 3, is deposited on a substrate 2, the SiO2 film 3 is etched to form a via hole 31 therein, and then, a top dielectric film, e.g., a CF film 4, is deposited on the top face of the SiO2 film 3. If the CF film is deposited by activating a thin-film deposition material having a bad embedded material, e.g., C6F6 gas, as a plasma, the CF film 4 can be deposited on the top face of the SiO2 film 3 while inhibiting the CF film from being embedded into the via hole 31. Subsequently, by etching the CF film 4 to form a groove 41 therein, it is possible to easily produce a dual damascene shape wherein the groove 41 is integrated with the via hole 31.

公开(公告)号：EP1280194A2

公开(公告)日：2003-01-29

申请号：EP02013435.9

申请日：2002-06-13

Applicant: Canon Sales Co., Inc. ,  Semiconductor Process Laboratory Co., Ltd.

Inventor： Shioya, Yoshimi ,  Nishimoto, Yuhko ,  Suzuki, Tomomi ,  Ikakura, Hiroshi ,  Maeda, Kazuo

IPC: H01L21/316

CPC classification number: H01L21/76834 ,  C23C16/0272 ,  C23C16/401 ,  C23C16/5096 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2221/1036

Abstract: The present invention relates to a manufacturing method of a semiconductor device in which a barrier insulating film and a main insulating film having low relative dielectric constant are sequentially formed while a wiring mainly consisting of copper film is coated. Its constitution includes the steps of: forming the barrier insulating film 35a on a substrate 21 subject to deposition, in which an electric power having a first frequency (f1) is applied to a first film forming gas containing at least silicon-containing gas and oxygen-containing gas to transform said first film forming gas into plasma and to cause reaction; and forming the main insulating film 35b having low relative dielectric constant on the barrier insulating film 35a, in which an electric power having a second frequency (f2) higher than the first frequency (f1) is applied to a second film forming gas containing at least the silicon-containing gas and the oxygen-containing gas to transform the second film forming gas into plasma and to cause reaction.

Abstract translation: 本发明涉及一种半导体器件的制造方法，其中依次形成具有低相对介电常数的阻挡绝缘膜和主绝缘膜，同时涂布主要由铜膜组成的布线。 其构成包括以下步骤：在要沉积的基板21上形成阻挡绝缘膜35a，其中将具有第一频率（f1）的电力施加到包含至少含硅气体和氧气的第一成膜气体 将所述第一成膜气体转化为等离子体并引起反应; 并且在阻挡绝缘膜35a上形成具有低相对介电常数的主绝缘膜35b，其中将具有比第一频率（f1）高的第二频率（f2）的电力施加到第二成膜气体，所述第二成膜气体至少包含 含硅气体和含氧气体将第二成膜气体转化为等离子体并引起反应。

公开(公告)号：EP0373344A2

公开(公告)日：1990-06-20

申请号：EP89120347.3

申请日：1989-11-03

Applicant: International Business Machines Corporation

Inventor： Cronin, John Edward ,  Kaanta, Carter Welling ,  Leach, Michael Albert

IPC: H01L21/90

CPC classification number: H01L21/76808 ,  H01L21/32053 ,  H01L21/4846 ,  H01L21/76877 ,  H01L21/7688 ,  H01L2221/1031 ,  H01L2221/1036 ,  H05K3/0017 ,  H05K3/06 ,  H05K3/107 ,  H05K3/4644 ,  Y10T29/49158

Abstract: A method for forming an electrically conductive line between two layers of insulating material and method for connecting the line through both layers of the insulating material to the opposite surfaces is provided. In the method, first, second and third layers (10, 20, 28) of insulating material are provided wherein said first and third layers are separated by said second layer of insulating material which is different in etch rate from the first and third layers. The edge portion of all three layers is exposed and the insulating layer of the second material is selectively etched to remove the revealed edge portion and provide a slot (36) between the first (10) and third (28) layers of insulating material. Also openings (38) are provided in both the first and third layers of insulating material which communicate with the slot and extend respectively through the layers of the first and third insulating material. Thereafter, a conductive material such as tungsten is deposited in the slot and the openings and also on the face of the stacked insulating material. Finally, the excess tungsten is removed from the faces of the insulating material of the first and third layers leaving a conductive line sandwiched between the first and third insulating layers of the material; also metal remains in the openings formed to thereby form conductive studs extending from the line to the opposite surfaces of the insulating material sandwich so formed.

Abstract translation: 提供了一种用于在绝缘材料和方法，用于绝缘材料的两个层连接到删除线的相对表面的两个层之间的导电线形成方法。 在绝缘材料制成，第一，第二和第三层（10，20，28）的方法被提供worin所述第一和第三层是由绝缘材料制成的所有这是在从所述第一层和第三层的蚀刻速率不同的所述第二层分离。 所有三个层的边缘部分被暴露，所述第二材料构成的绝缘层被选择性地蚀刻，以除去揭示边缘部分和提供第一（10）之间的槽（36）和绝缘材料的第三（28）层。 所以在与该槽相通并分别通过第一和第三绝缘材料的开口（38）的层延伸的绝缘材料。第一层和第三层提供。 有后，导电材料：诸如钨在插槽和开口等层叠的绝缘材料的表面沉积。 最后，将过量的钨从第一层和第三层在离开夹在材料的第一和第三绝缘层之间的导电线的绝缘材料的面除去 所以金属残留在形成为从而开口形成导电柱从线到如此形成的绝缘材料夹层结构的相对的表面延伸。