公开(公告)号：WO2012037517A2

公开(公告)日：2012-03-22

申请号：PCT/US2011052028

申请日：2011-09-16

Applicant: ALTERA CORP ,  DING WEIQI ,  PAN MINGDE ,  LI PENG ,  SHUMARAYEV SERGEY ,  SHIMANOUCHI MASASHI

Inventor： DING WEIQI ,  PAN MINGDE ,  LI PENG ,  SHUMARAYEV SERGEY ,  SHIMANOUCHI MASASHI

IPC: H04L1/00 ,  G01R29/02

CPC classification number: H04L1/203 ,  G01R31/3171

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract translation: 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

公开(公告)号：WO2011100207A3

公开(公告)日：2011-11-17

申请号：PCT/US2011023964

申请日：2011-02-08

Applicant: ALTERA CORP ,  JIANG XIAOHONG ,  SHI HONG

Inventor： JIANG XIAOHONG ,  SHI HONG

IPC: H01L23/48 ,  H01L21/60 ,  H01L23/535

CPC classification number: H01L23/66 ,  H01L23/50 ,  H01L23/5286 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package. In the first row, ground contacts alternate with contacts for receiving differential signals and in the second row ground contacts alternate with contacts for transmitting differential signals. The third row of contacts is located between the first and second rows and contains contacts for receiving differential signals that alternate with contacts for transmitting differential signals. The ground contacts in the second row are offset by one column from the ground contacts in the first row. In a second embodiment, the receiving contacts in the third row are in the same column as the receiving contacts in the first row; and the transmitting contacts in the third row are in the same column as the transmitting contacts in the second row. In a third embodiment, the contacts in the third row are offset by one column from the corresponding contacts in the first or second rows. Each pair of contacts for receiving differential signals is formed by a contact in the first row and an adjacent contact in the third row; and each pair of contacts for transmitting differential signals is formed by a contact in the second row and an adjacent contact in the third row.

Abstract translation: 在一个实施例中，信令和接地触点位于沿着诸如BGA封装的互连封装的至少一个边缘的至少两个平行直线排中。 在一行中，多个接地触点中的每一个位于用于接收差分信号的两对触点之间。 在第二行中，多个接地触点中的每一个位于用于传输差分信号的两对触点之间，并且第二行中的接地触点与第一行中的接地触点偏移一列。 结果，信令对与接地触点的比例为2：2。 还可以使用另外的行对。 在其他实施例中，信号和接地触点沿着包装的至少一个边缘位于三个平行的直线行中。 在第一行中，接地触点与用于接收差分信号的触点交替，而在第二行中，接地触点与用于传输差分信号的触点交替。 第三行触点位于第一行和第二行之间，并且包含用于接收与用于传输差分信号的触点交替的差分信号的触点。 第二行的接地触点与第一行的接地触点偏移一列。 在第二实施例中，第三行中的接收触点与第一行中的接收触点在同一列中; 并且第三行中的发送触点与第二行中的发送触点在同一列中。 在第三实施例中，第三行中的触点从第一行或第二行中的对应触点偏移一列。 用于接收差分信号的每对触点由第一行中的触点和第三行中的相邻触点形成; 并且用于传输差分信号的每对触点由第二行中的触点和第三行中的相邻触点形成。

公开(公告)号：WO2011091073A3

公开(公告)日：2011-11-17

申请号：PCT/US2011021762

申请日：2011-01-19

Applicant: ALTERA CORP ,  CHONG YAN ,  HUANG JOSEPH ,  NAGARAJAN PRADEEP ,  SUNG CHIAKANG

Inventor： CHONG YAN ,  HUANG JOSEPH ,  NAGARAJAN PRADEEP ,  SUNG CHIAKANG

IPC: G11C7/22 ,  G11C7/10

CPC classification number: H03K5/1565 ,  H03K5/151 ,  H03K5/1534 ,  H03K2005/00019

Abstract: Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

Abstract translation: 公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 该IC包括分离器电路，其被耦合以接收时钟信号。 时钟信号被分成两个不同的时钟信号。 其中一个时钟信号是另一个的反转版本。 延迟电路被耦合到每个时钟信号。 每个延迟电路产生对应的时钟信号的延迟版本。 校正器电路被耦合以接收时钟信号的延迟版本。 校正器电路产生具有校正占空比的时钟输出信号。

公开(公告)号：WO2011112739A2

公开(公告)日：2011-09-15

申请号：PCT/US2011027780

申请日：2011-03-09

Applicant: ALTERA CORP ,  CHEN SHUXIAN ,  WATT JEFFREY T

Inventor： CHEN SHUXIAN ,  WATT JEFFREY T

IPC: H01Q1/24 ,  H01Q1/38

CPC classification number: H01F17/0013 ,  H01F2017/0046 ,  H01F2017/0086

Abstract: An integrated circuit inductor may have upper and lower loop-shaped line portions that are connected in series. The upper and lower portions may have 45° bends that form hexagonal or octagonal loops. Each loop portion may have one or more turns. Intervening metal-free regions of metal routing layers may be formed between the two layers to reduce capacitive coupling. Each loop portion may have sets of two or more metal lines shorted in parallel by vias. The upper and lower loops may be laterally offset or nested to reduce capacitive coupling.

Abstract translation: 集成电路电感器可以具有串联连接的上下环形线部分。 上部和下部可以具有形成六边形或八边形环的45°弯曲。 每个回路部分可以具有一个或多个匝。 可以在两层之间形成金属布线层的不间断的金属区域，以减少电容耦合。 每个环部分可以具有由通孔平行短路的两条或多条金属线组。 上下环路可以横向偏移或嵌套以减小电容耦合。

公开(公告)号：WO2011046809A2

公开(公告)日：2011-04-21

申请号：PCT/US2010051880

申请日：2010-10-08

Applicant: ALTERA CORP ,  JIANG XIAHONG ,  SHI HONG ,  LIU HUI ,  XIE YUANLIN

Inventor： JIANG XIAHONG ,  SHI HONG ,  LIU HUI ,  XIE YUANLIN

IPC: H01L23/12 ,  H01L23/48 ,  H01L23/485

CPC classification number: H01L23/5383 ,  H01L23/12 ,  H01L23/48 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/014

Abstract: An integrated circuit (IC) package substrate with non-uniform dielectric layers is disclosed. The IC package substrate is a multilayer package substrate that has dielectric layers and metal layers stacked up alternately. The dielectric layers in the package substrate have different thickness. The metal layers may be ground, signal or power layers. A thicker dielectric layer is placed in between a signal layer and a power layer in the package substrate. The thicker dielectric layer may be at least twice as thick as other dielectric layers in the package substrate. The thicker dielectric layer may provide better impedance control in the package substrate.

Abstract translation: 公开了具有不均匀电介质层的集成电路（IC）封装基板。 IC封装基板是具有交替堆叠的电介质层和金属层的多层封装基板。 封装衬底中的电介质层具有不同的厚度。 金属层可以是接地，信号或功率层。 在封装衬底中的信号层和功率层之间放置较厚的介电层。 较厚的电介质层可以是封装衬底中其它电介质层的至少两倍。 较厚的介电层可以在封装衬底中提供更好的阻抗控制。

公开(公告)号：WO2010090820A3

公开(公告)日：2010-11-18

申请号：PCT/US2010021430

申请日：2010-01-19

Applicant: ALTERA CORP ,  TOONG TEIK TIONG ,  TAN LOON KWANG

Inventor： TOONG TEIK TIONG ,  TAN LOON KWANG

IPC: H01L23/62

CPC classification number: H01L23/642 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.

Abstract translation: 公开了一种集成电路（IC）封装，其具有放置在管芯表面上的多个片式电容器。 芯片电容器可以放置在具有处理衬底层的管芯的顶部上。 在芯片顶部放置片状电容器可能会减小所需的封装基板的尺寸。 可以使用一根或多根导线将覆盖层上的片状电容器连接到封装基板。 IC封装可以包括盖和放置在管芯顶部的热界面材料（TIM）。 盖可以成形为使得盖的突出部分直接通过TIM接触模具以改善散热。

公开(公告)号：WO2010045081A3

公开(公告)日：2010-07-22

申请号：PCT/US2009059874

申请日：2009-10-07

Applicant: ALTERA CORP ,  VIJAYARAGHAVAN DIVYA ,  WORTMAN CURT ,  LEE CHONG H

Inventor： VIJAYARAGHAVAN DIVYA ,  WORTMAN CURT ,  LEE CHONG H

IPC: H04B1/40

CPC classification number: H04B1/005 ,  G06F13/385 ,  H04L69/12 ,  H04L69/18

Abstract: Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer ("PCS") circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer ("PMA") circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent ("PMD") sub-layer circuitry.

Abstract translation: 本公开的实施例包括包括接收和/或发送电路的可配置布置的多协议收发器。 可以选择性地配置示例性收发器以有效地发送和/或接收对应于多个高速通信协议中的选择一个的数据通信。 所公开的另一更具体的实施例包括通过链路范围物理编码子层（“PCS”）电路的可配置数据路径，包括链路范围时钟补偿，编码/解码以及加扰/解扰频电路和通道条带/去条纹电路; 可配置数据路径还包括通道宽电路，包括时钟补偿，编码/解码，接收块同步和物理介质访问子层（“PMA”）电路，并且还包括耦合到物理介质的位复用/解复用电路 从属（“PMD”）子层电路。

公开(公告)号：WO2010051244A2

公开(公告)日：2010-05-06

申请号：PCT/US2009062028

申请日：2009-10-26

Applicant: ALTERA CORP ,  WONG WILSON ,  CHAN ALLEN ,  SHUMARAYEV SERGEY

Inventor： WONG WILSON ,  CHAN ALLEN ,  SHUMARAYEV SERGEY

IPC: G01R31/28 ,  H03M1/12

CPC classification number: G01R31/3167

Abstract: An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

Abstract translation: 介绍了一种能够监测模拟模块内部模拟电压的集成电路。 该集成电路有一个模拟测试多路复用器（mux），其输入端连接到模拟模块内部感兴趣的模拟电压。 模拟测试多路复用器将选定的模拟电压从模拟模块引导至模拟测试多路复用器的输出。 该集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。 集成电路还包括模数转换器，用于将来自模拟测试多路复用器的选定模拟电压转换为数字表示。

公开(公告)号：WO2010014355A3

公开(公告)日：2010-04-08

申请号：PCT/US2009049713

申请日：2009-07-06

Applicant: ALTERA CORP ,  RATNAKUMAR ALBERT ,  XIANG QI ,  TUNG JEFFREY XIAOQI

Inventor： RATNAKUMAR ALBERT ,  XIANG QI ,  TUNG JEFFREY XIAOQI

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L29/94

Abstract: A varactor may have a first terminal connected to a gate. The gate may be formed from a p-type polysilicon gate conductor. The gate may also have a gate insulator formed from a layer of insulator such as silicon oxide. The gate insulator may be located between the gate conductor and a body region. Source and drain contact regions may be formed in a silicon body region. The body region and the source and drain may be doped with n-type dopant. The varactor may have a second terminal connected to the n-type source and drain. A control voltage may be used to adjust the level of capacitance produced by the varactor between the first and second terminals. A positive control voltage may produce a larger capacitance than a negative control voltage. Application of the negative control voltage may produce a depletion layer in the p+ polysilicon gate layer.

Abstract translation: 变容二极管可以具有连接到门的第一端子。 栅极可以由p型多晶硅栅极导体形成。 栅极还可以具有由诸如氧化硅的绝缘体层形成的栅极绝缘体。 栅极绝缘体可以位于栅极导体与本体区域之间。 源极和漏极接触区域可以形成在硅本体区域中。 体区和源极和漏极可以掺杂有n型掺杂剂。 变容管可以具有连接到n型源极和漏极的第二端子。 可以使用控制电压来调整由第一和第二端子之间的变容二极管产生的电容的电平。 正控制电压可能产生比负控制电压更大的电容。 施加负控制电压可能在p +多晶硅栅极层中产生耗尽层。

公开(公告)号：WO2010033436A2

公开(公告)日：2010-03-25

申请号：PCT/US2009056753

申请日：2009-09-11

Applicant: ALTERA CORP ,  HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

Inventor： HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03L7/193 ,  H03L7/087

CPC classification number: H03L7/099 ,  H03L7/18

Abstract: A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

Abstract translation: 一种电路包括相位检测电路，时钟信号生成电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以生成控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值以产生第二分频信号。 第一和第二分频信号在不同的时间间隔期间作为反馈信号被路由到相位检测电路。