公开(公告)号：WO2012037517A2

公开(公告)日：2012-03-22

申请号：PCT/US2011052028

申请日：2011-09-16

Applicant: ALTERA CORP ,  DING WEIQI ,  PAN MINGDE ,  LI PENG ,  SHUMARAYEV SERGEY ,  SHIMANOUCHI MASASHI

Inventor： DING WEIQI ,  PAN MINGDE ,  LI PENG ,  SHUMARAYEV SERGEY ,  SHIMANOUCHI MASASHI

IPC: H04L1/00 ,  G01R29/02

CPC classification number: H04L1/203 ,  G01R31/3171

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract translation: 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

公开(公告)号：WO2011133565A3

公开(公告)日：2011-10-27

申请号：PCT/US2011/033071

申请日：2011-04-19

Applicant: ALTERA CORPORATION ,  LI, Peng ,  SHIMANOUCHI, Masashi ,  TRAN, Thungoc, M. ,  SHUMARAYEV, Sergey

Inventor： LI, Peng ,  SHIMANOUCHI, Masashi ,  TRAN, Thungoc, M. ,  SHUMARAYEV, Sergey

IPC: G06F9/455 ,  G06F17/50 ,  G06F11/25

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two- dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

公开(公告)号：WO2012021332A3

公开(公告)日：2012-04-12

申请号：PCT/US2011046239

申请日：2011-08-02

Applicant: ALTERA CORP ,  LI PENG ,  SHIMANOUCHI MASASHI ,  SHUMARAYEV SERGEY ,  DING WEIQI ,  NARAYAN SRIRAM ,  CHOW DANIEL TUN LAI ,  PAN MINGDE

Inventor： LI PENG ,  SHIMANOUCHI MASASHI ,  SHUMARAYEV SERGEY ,  DING WEIQI ,  NARAYAN SRIRAM ,  CHOW DANIEL TUN LAI ,  PAN MINGDE

IPC: G01R31/303

CPC classification number: G01R31/31709 ,  G01R31/3171 ,  G01R31/31716 ,  H04L7/0337

Abstract: An integrated circuit ("IC") may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate ("BER") analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract translation: 集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

公开(公告)号：WO2012021332A2

公开(公告)日：2012-02-16

申请号：PCT/US2011/046239

申请日：2011-08-02

Applicant: ALTERA CORPORATION ,  LI, Peng ,  SHIMANOUCHI, Masashi ,  SHUMARAYEV, Sergey ,  DING, Weiqi ,  NARAYAN, Sriram ,  CHOW, Daniel Tun Lai ,  PAN, Mingde

Inventor： LI, Peng ,  SHIMANOUCHI, Masashi ,  SHUMARAYEV, Sergey ,  DING, Weiqi ,  NARAYAN, Sriram ,  CHOW, Daniel Tun Lai ,  PAN, Mingde

IPC: G01R31/303

CPC classification number: G01R31/31709 ,  G01R31/3171 ,  G01R31/31716 ,  H04L7/0337

Abstract: An integrated circuit ("IC") may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate ("BER") analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract translation: 集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于传输具有可选抖动，可选噪声和/或可控可变驱动强度的串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这样的信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以在各种模式下工作，以执行或至少仿真示波器，误码率测试仪等的功能，用于测试有关抖动容限，噪声容限等的信号和电路。

公开(公告)号：WO2012037517A3

公开(公告)日：2012-03-22

申请号：PCT/US2011/052028

申请日：2011-09-16

Applicant: ALTERA CORPORATION ,  DING, Weiqi ,  PAN, Mingde ,  LI, Peng ,  SHUMARAYEV, Sergey ,  SHIMANOUCHI, Masashi

Inventor： DING, Weiqi ,  PAN, Mingde ,  LI, Peng ,  SHUMARAYEV, Sergey ,  SHIMANOUCHI, Masashi

IPC: H04L1/00 ,  G01R29/02

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

公开(公告)号：WO2011133565A2

公开(公告)日：2011-10-27

申请号：PCT/US2011033071

申请日：2011-04-19

Applicant: ALTERA CORP ,  LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

Inventor： LI PENG ,  SHIMANOUCHI MASASHI ,  TRAN THUNGOC M ,  SHUMARAYEV SERGEY

IPC: G06F9/455 ,  G06F11/25 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two- dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括诸如传递函数，概率密度函数和眼睛特征的特征函数。 链接仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

公开(公告)号：WO2003071297A1

公开(公告)日：2003-08-28

申请号：PCT/US2003/005227

申请日：2003-02-18

Applicant: NPT EST, INC. ,  SHIMANOUCHI, Masashi ,  MAASSEN, Howard

Inventor： SHIMANOUCHI, Masashi ,  MAASSEN, Howard

IPC: G01R31/28

CPC classification number: G01R31/2844

Abstract: Method and apparatus for circuit testing with signal paths providing multiple test configurations. Circuitry for use in testing elelectronic circuits includes switching circuitry operable to be controlled to make one of a first signal path and a second signal path. The first signal path is configured to carry a signal between a first node and a second node. The second signal path is configured to carry a signal between the first node and a third node. Each of the signal paths includes a portion that is located in pin electronics. The first node is connectable to a first pin of a device under test. The second node is connectableto a second pin of a device under test. The third node is connectable to an electronic instrument.

Abstract translation: 具有提供多种测试配置的信号路径进行电路测试的方法和装置。 用于测试电子电路的电路包括可操作以控制以形成第一信号路径和第二信号路径之一的开关电路。 第一信号路径被配置为在第一节点和第二节点之间传送信号。 第二信号路径被配置为在第一节点和第三节点之间传送信号。 每个信号路径包括位于引脚电子部件中的部分。 第一个节点可连接到被测设备的第一个引脚。 第二个节点可连接到被测设备的第二个引脚。 第三节点可连接到电子仪器。