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    속도가변형아날로그데이터취득회로
    87.
    发明授权
    속도가변형아날로그데이터취득회로 失效
    速度可变的模拟数据采集电路

    公开(公告)号：KR1019900006394B1

    公开(公告)日：1990-08-30

    申请号：KR1019870000418

    申请日：1987-01-20

    Applicant: 삼성전자주식회사

    Inventor： 김용근 ,  이성화 ,  남병덕

    IPC: G06F17/00 ,  G06F3/05

    Abstract: The analog data acquistion circuit converts the analog signal generated from transient state to steady state into digital signal. Tri-state outters (20,23,24) stores the data provided from and A/D converter (10) into a RAM (30) of which addresses correspond to the data provided from counters (40-43). A programmable interval timer (50) provides write signal to the RAM (30) and clock pulses to a timer (40) and the A/D converter (10). A NAND gate (80) provides an interrupt signal to a CPU (70) after combining carry signal of a counter (43) and output of a decoder (60). Tri-state buffers (21,22) makes the CPU recognise the data after reading the data stored in the RAM (30) with address signal provided from the CPU.

    Abstract translation: 模拟数据采集电路将从瞬态产生的模拟信号转换为稳态转换为数字信号。 三态输出器（20,23,24）将从A / D转换器（10）提供的数据存储到与计数器（40-43）提供的数据相对应的地址的RAM（30）中。 可编程间隔定时器（50）向RAM（30）提供写入信号，并将时钟脉冲提供给定时器（40）和A / D转换器（10）。 NAND门（80）在组合计数器（43）的进位信号和解码器（60）的输出之后，向CPU（70）提供中断信号。 三态缓冲器（21,22）使CPU在从CPU提供的地址信号读取存储在RAM（30）中的数据之后识别数据。

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