公开(公告)号：KR1020120026881A

公开(公告)日：2012-03-20

申请号：KR1020100089058

申请日：2010-09-10

Applicant: 삼성전자주식회사

Inventor： 황성민 ,  김한수 ,  강창석 ,  조원석 ,  심재주

IPC: H01L27/10 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11578 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/0688

Abstract: PURPOSE: Three dimensional semiconductor memory devices are provided to perform easily a planarization process of 3D semiconductor memory device by forming a first vertical type activity patterns more than a second vertical type activity patterns. CONSTITUTION: A first laminate structure(115) comprises a first insulting pattern(105) and a first gate pattern(110). A plurality of first vertical type activity patterns(130) passes through the first laminate structure. A first data store film(125) is formed between the sidewall and the first insulating pattern(105) of the first vertical type activity pattern. A second laminate structure(215) comprises a second insulating pattern(205) and a second gate pattern(210). A plurality of second vertical type activity patterns(230) passes through the second laminate structure.

Abstract translation: 目的：提供三维半导体存储器件，以通过形成多于第二垂直类型活动图案的第一垂直类型活动图案来容易地执行3D半导体存储器件的平坦化处理。 构成：第一层压结构（115）包括第一绝缘图案（105）和第一栅极图案（110）。 多个第一垂直型活动图案（130）穿过第一层压结构。 第一数据存储膜（125）形成在第一垂直型活动图案的侧壁和第一绝缘图案（105）之间。 第二层压结构（215）包括第二绝缘图案（205）和第二栅极图案（210）。 多个第二垂直型活动图案（230）穿过第二层压结构。

公开(公告)号：KR1020120000900A

公开(公告)日：2012-01-04

申请号：KR1020100061421

申请日：2010-06-28

Applicant: 삼성전자주식회사

Inventor： 김기현 ,  김한수 ,  장재훈 ,  심선일 ,  박철민

IPC: G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30

Abstract: PURPOSE: A nonvolatile memory device, a reading method thereof and a memory system including the same are provided to prevent alternative reading by performing a reading which includes boosting. CONSTITUTION: In a nonvolatile memory device, a reading method thereof and a memory system including the same, a bit line is pre-charged(S110). String selection lines are set up(S120). Word lines are set up(S130). Ground selection lines are set up(S140). A bit line voltage is applied to the bit lines. A first string selection line voltage is applied to at least one string line. A second string selection line voltage is applied to at least one non-selected string line. A read voltage is applied to the word lines. A first ground selection line voltage is applied to at least one ground line. A second ground selection line voltage is applied to at least one non-selected ground line.

Abstract translation: 目的：提供非易失性存储器件及其读取方法和包括该非易失性存储器件的存储器系统，以通过执行包括升压的读取来防止替代读取。 构成：在非易失性存储器件中，其读取方法和包括该非易失性存储器件的存储器系统，位线被预充电（S110）。 设置字符串选择行（S120）。 字线设置（S130）。 设置接地选择线（S140）。 位线电压施加到位线。 第一串选择线电压被施加到至少一个串线。 第二弦选择线电压被施加到至少一个未选择的弦线。 读取电压被施加到字线。 第一接地选择线电压被施加到至少一个接地线。 第二接地选择线电压施加到至少一个未选择的接地线。

公开(公告)号：KR1020110133926A

公开(公告)日：2011-12-14

申请号：KR1020100053600

申请日：2010-06-07

Applicant: 삼성전자주식회사

Inventor： 황성민 ,  김한수 ,  심선일

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L21/823487 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor memory device of a vertical structure is provided to increase an insulation breaking voltage between transistors vertical to a common source line, thereby increasing the performance of the device. CONSTITUTION: A substrate(100) comprises a first area and a second area. A semiconductor area(120) is perpendicularly expanded from the first area of the substrate. Gate electrodes(150) are vertically separated on the first area of the substrate. Gate dielectric films(140) are arranged between the semiconductor area and the gate electrodes. A substrate contact electrode(110) is vertically connected to the second area of the substrate.

Abstract translation: 目的：提供垂直结构的半导体存储器件以增加垂直于公共源极线的晶体管之间的绝缘断开电压，从而提高器件的性能。 构成：衬底（100）包括第一区域和第二区域。 半导体区域（120）从衬底的第一区域垂直地扩展。 栅极电极（150）在衬底的第一区域上垂直分离。 栅介质膜（140）布置在半导体区域和栅电极之间。 衬底接触电极（110）垂直连接到衬底的第二区域。

公开(公告)号：KR1020110104317A

公开(公告)日：2011-09-22

申请号：KR1020100023398

申请日：2010-03-16

Applicant: 삼성전자주식회사

Inventor： 정재훈 ,  김한수 ,  조원석 ,  장재훈

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11578 ,  H01L27/11582 ,  H01L29/7926 ,  H01L21/823431 ,  H01L27/0688

Abstract: 수직 채널 구조의 비휘발성 메모리 소자가 제공된다. 본 발명의 실시 예에 따른 비휘발성 메모리 소자는 제1 방향으로 연장되는 주면을 가지며, 소자 영역과 연결 영역이 정의된 기판, 소자 영역 상에서 제1 방향에 대하여 수직인 제2 방향으로 연장되어 있는 반도체 기둥들, 반도체 기둥들의 측벽을 따라 기판 상으로 수직 신장하고, 복수의 메모리셀들이 배치된 복수의 낸드 셀 스트링들, 복수의 낸드 셀 스트링들의 복수의 메모리셀들을 구성하며, 제1 방향으로 연장되는 복수의 게이트 라인들 및 연결 영역 상에 형성되며, 복수의 게이트 라인들과 연결되고 제1 방향으로 연장되는 수평부, 및 수평부와 연결되며 제2 방향으로 연장되는 기둥부를 포함하는 복수개의 도전성의 게이트 연결부를 포함하는 게이트 연결부 군을 포함하며, 게이트 연결부는 수평부와 기둥부에 걸쳐서 형성되고 지지절연층으로 채워 진 개구부를 포함한다.

公开(公告)号：KR1020110072917A

公开(公告)日：2011-06-29

申请号：KR1020090130030

申请日：2009-12-23

Applicant: 삼성전자주식회사 ,  한양대학교 산학협력단

Inventor： 권문석 ,  김한수 ,  최재만 ,  송민상 ,  위성복 ,  백운규 ,  이진헌

IPC: H01M4/133 ,  H01M10/0525

CPC classification number: H01M4/133 ,  H01M4/625 ,  H01M10/0525

Abstract: PURPOSE: A carbon conductive material is provided to ensure excellent particle dispersibility within an electrode composition and to improve the conductivity of the electrode. CONSTITUTION: A carbon conductive material includes a carboxy group and an amine group. The carboxy group and the amine group are ion-bonded in a COO^- and NH^(3+) state. The carboxy group is bonded through UV-ozone treatment, high oxidation treatment, acid treatment, plasma acid treatment or immersion in an acidic solution of pH 6 or less. The electrode composition comprises an electrode active material, binder and carbon-based electrical conducting material.

Abstract translation: 目的：提供碳导电材料以确保在电极组合物内优异的颗粒分散性并改善电极的导电性。 构成：碳导电材料包括羧基和胺基。 羧基和胺基以COO 2 - 和NH 3（3+）状态离子键合。 羧基通过UV-臭氧处理，高氧化处理，酸处理，等离子体酸处理或在pH6以下的酸性溶液中浸渍而结合。 电极组合物包括电极活性材料，粘合剂和碳基导电材料。

公开(公告)号：KR1020110003764A

公开(公告)日：2011-01-13

申请号：KR1020090061204

申请日：2009-07-06

Applicant: 삼성전자주식회사

Inventor： 황성민 ,  김한수 ,  조원석 ,  장재훈

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/768 ,  H01L27/11578 ,  H01L29/6656 ,  H01L21/28141

Abstract: PURPOSE: A method for manufacturing a nonvolatile memory device is provided to reduce the contact resistance of a common source-line by forming a highly doped impurity region and/or a metal side layer on a part of a semiconductor substrate in contact with a metal-line. CONSTITUTION: A first insulating pillar(140) is formed on a first part of a substrate(100). A cell string unit(11) is vertically arranged along the lateral side of the first insulating pillar. An impurity region(150) is formed at a second part of the semiconductor substrate between cell string units. A spacer(170) arranged at the sidewall of the cell string unit is formed on a part of the impurity region. A conductive line(180) is formed on the impurity region between spacers.

Abstract translation: 目的：提供一种用于制造非易失性存储器件的方法，用于通过在半导体衬底的与金属层间接触的部分上形成高掺杂杂质区域和/或金属侧层来降低公共源极线的接触电阻， 线。 构成：在基板（100）的第一部分上形成第一绝缘柱（140）。 电池串单元（11）沿着第一绝缘柱的横向方向垂直布置。 在单元串单元之间的半导体衬底的第二部分处形成杂质区（150）。 布置在电池串单元的侧壁处的间隔物（170）形成在杂质区域的一部分上。 在间隔物之间​​的杂质区域上形成导线（180）。

公开(公告)号：KR1020100093350A

公开(公告)日：2010-08-25

申请号：KR1020090012497

申请日：2009-02-16

Applicant: 삼성전자주식회사

Inventor： 김기현 ,  김한수 ,  조원석 ,  김진호 ,  장재훈 ,  손병근

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L21/02225 ,  H01L21/2253 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/66348

Abstract: PURPOSE: A semiconductor device and a forming method thereof are provided to efficiently perform writing and erasing operations by forming a cell string including a source/drain region doped with a dopant. CONSTITUTION: An insulation pattern(112) and a gate pattern(147) are alternatively laminated on a substrate(100). An active pattern(133) is extended to the upper side along the sidewall of the gate patterns on the substrate. A data storage pattern is interposed between the gate pattern and the active pattern. A source/drain region(138) doped with the dopant is arranged inside the active pattern. A semiconductor pattern(122) is arranged on an undercut region(119).

Abstract translation: 目的：提供半导体器件及其形成方法，以通过形成包括掺杂有掺杂剂的源极/漏极区域的单元串来有效地执行写入和擦除操作。 构成：绝缘图案（112）和栅极图案（147）交替层压在基板（100）上。 有源图案（133）沿着衬底上的栅极图案的侧壁延伸到上侧。 在栅极图案和有源图案之间插入数据存储图案。 掺杂有掺杂剂的源极/漏极区域（138）布置在有源图案的内部。 半导体图案（122）布置在底切区域（119）上。

公开(公告)号：KR1020100044087A

公开(公告)日：2010-04-29

申请号：KR1020090085075

申请日：2009-09-09

Applicant: 삼성전자주식회사 ,  한양대학교 산학협력단

Inventor： 최재만 ,  김한수 ,  권문석 ,  백운규 ,  김현호 ,  위성복 ,  이진헌

IPC: H01M4/36 ,  H01M4/02 ,  H01M10/04

Abstract: PURPOSE: An electrode ink composition for ink-jet printing is provided to manufacture electrode with minute patterns by an ink jet printing method. CONSTITUTION: An electrode ink composition for ink-jet printing comprises: an electrode active material, and a solvent, wherein the solvent further comprises a first solvent having a boiling point in a range of about 150 to about 170deg.C at 1 atm, and a surface tension of 30 dyne/cm or more at 25deg.C. The first solvent is a solvent comprising an amide group. The electrode composition for the inkjet print comprises the electrode active material and solvent.

Abstract translation: 目的：提供一种用于喷墨打印的电极油墨组合物，通过喷墨打印方法制造具有微小图案的电极。 构成：用于喷墨打印的电极油墨组合物包括：电极活性材料和溶剂，其中所述溶剂还包含沸点在大气压约150至约170℃范围内的第一溶剂，以及 25℃下表面张力30达因/厘米或更高。 第一溶剂是包含酰胺基的溶剂。 用于喷墨打印的电极组合物包括电极活性材料和溶剂。

公开(公告)号：KR1020100024257A

公开(公告)日：2010-03-05

申请号：KR1020080083026

申请日：2008-08-25

Applicant: 삼성전자주식회사

Inventor： 정재훈 ,  정순문 ,  김한수 ,  장재훈

IPC: G11C16/14 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483

Abstract: PURPOSE: A non-volatile memory device and an erase method of the same are provided to perform the erase operation of cell transistors by applying voltages through the gates of a non-volatile memory cell transistors and a semiconductor substrate. CONSTITUTION: Semiconductor substrates(312, 314) are successively stacked. Non-volatile memory cell transistors(TM1_1, TM2_1, TM3_1, TM4_1) are respectively formed in a row on the upper side of the semiconductor substrates. A plurality of word-lines is connected to a plurality of the non-volatile memory cell transistors. A plurality of non-volatile memory cells formed on each semiconductor substrate is grouped into two or more memory cell blocks. A first voltage is applied to a semiconductor substrate which belongs to a memory cell block to be erased.

Abstract translation: 目的：提供非易失性存储器件及其擦除方法，以通过非易失性存储单元晶体管和半导体衬底的栅极施加电压来执行单元晶体管的擦除操作。 构成：依次层叠半导体基板（312,314）。 非易失性存储单元晶体管（TM1_1，TM2_1，TM3_1，TM4_1）分别形成在半导体衬底的上侧上的一行中。 多个字线连接到多个非易失性存储单元晶体管。 形成在每个半导体衬底上的多个非易失性存储单元被分组成两个或更多个存储单元块。 将第一电压施加到属于要擦除的存储单元块的半导体衬底。

公开(公告)号：KR1020100004770A

公开(公告)日：2010-01-13

申请号：KR1020080065118

申请日：2008-07-04

Applicant: 삼성전자주식회사

Inventor： 김한수 ,  장재훈 ,  조후성

IPC: H01L27/10 ,  H01L27/115

CPC classification number: H01L27/11551 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/2436 ,  H01L27/2463

Abstract: PURPOSE: A memory semiconductor device is provided to a single channel effect property by increasing the width of a transistor gate arranging on a base layer. CONSTITUTION: A memory semiconductor device comprises a first semiconductor layer(100) and a second semiconductor layer(200). The semiconductor layer is formed with a semiconductor wafer. The second semiconductor layer is formed with a semiconductor material layer. The first semiconductor layer and the second semiconductor layer are formed with the same semiconductor material. A first string structure(STR1) is formed on the semiconductor layer. A second string structure(STR2) is formed on the second semiconductor layer. The first string structure comprises a pair of first selecting transistors and a plurality of first memory transistors. The second string structure comprises a pair of second selection transistors and a plurality of second memory transistors.

Abstract translation: 目的：通过增加布置在基底层上的晶体管栅极的宽度，将单个沟道效应特性提供到存储器半导体器件。 构成：存储器半导体器件包括第一半导体层（100）和第二半导体层（200）。 半导体层由半导体晶片形成。 第二半导体层由半导体材料层形成。 第一半导体层和第二半导体层由相同的半导体材料形成。 在半导体层上形成第一串结构（STR1）。 在第二半导体层上形成第二串结构（STR2）。 第一串结构包括一对第一选择晶体管和多个第一存储晶体管。 第二串结构包括一对第二选择晶体管和多个第二存储晶体管。