公开(公告)号：KR1020080082715A

公开(公告)日：2008-09-12

申请号：KR1020070023332

申请日：2007-03-09

Applicant: 삼성전자주식회사

Inventor： 최인혁 ,  김민상 ,  윤은정 ,  이성영 ,  이지명

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  B82Y10/00

CPC classification number: H01L27/2463 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/7825

Abstract: A multi-bit electro-mechanical memory device and a method for manufacturing the same are provided to reduce power consumption by forming a first and second contact units at ends of a first cantilever electrode and a second cantilever electrode. A substrate(10) has a predetermined flat surface. A bit line(20) is formed in a first direction on the substrate. A lower word line(30) and a trap site(80) are insulated from the bit line and are formed in a second direction intersected with the first direction. A pad electrode is insulated from the lower word line and a sidewall of the trap site and is connected to the bit line. A cantilever electrode(50) is connected to the pad electrode. The cantilever electrode has a low air gap on an upper portion of the trap site and is floated in a first direction. The cantilever electrode is bended in a third direction perpendicular to the first and second directions by an electric field induced from a charge applied to the lower word line. A lower contact unit and an upper contact unit focus the charge induced from the cantilever electrode in response to the charge applied from the lower word line and the trap site. The lower contact unit and the upper contact unit are protruded to up and down of the third direction from an end of the cantilever electrode to reduce a bended distance of the cantilever electrode in the low air gap. An upper word line(40) has an upper air gap on an upper portion of the cantilever electrode and is formed in the second direction.

Abstract translation: 提供了一种多位机电存储器件及其制造方法，以通过在第一悬臂电极和第二悬臂电极的端部处形成第一和第二接触单元来降低功耗。 基板（10）具有预定的平坦表面。 在基板上沿第一方向形成位线（20）。 下字线（30）和陷阱位置（80）与位线绝缘，并且沿与第一方向相交的第二方向形成。 焊盘电极与下部字线和陷阱位置的侧壁绝缘，并连接到位线。 悬臂电极（50）连接到焊盘电极。 悬臂电极在捕获部位的上部具有低气隙并且沿第一方向漂浮。 通过从施加到下字线的电荷引起的电场，悬臂电极在垂直于第一和第二方向的第三方向上弯曲。 下接触单元和上触点单元响应于从下字线和陷阱位置施加的电荷来聚焦从悬臂电极引起的电荷。 下接触单元和上接触单元从悬臂电极的端部向第​​三方向上下突出，以减小悬臂电极在低气隙中的弯曲距离。 上部字线（40）在悬臂电极的上部具有上部气隙并沿第二方向形成。

公开(公告)号：KR100842730B1

公开(公告)日：2008-07-01

申请号：KR1020070004672

申请日：2007-01-16

Applicant: 삼성전자주식회사

Inventor： 김민상 ,  이성영 ,  김성민 ,  윤은정 ,  김동원 ,  박동건

IPC: H01L27/115 ,  H01L21/8247 ,  B82Y40/00

CPC classification number: G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16 ,  H01L29/0665 ,  H01L29/0673 ,  H01L21/76224

Abstract: A multi-bit electro-mechanical memory device and a manufacturing method thereof are provided to increase or maximize an integration degree thereof by forming a cell array of a matrix type. A substrate(10) includes a predetermined flat surface. A lower bit line(20) is formed in a first direction on the substrate. A lower word line(30) and a trap site(80) are formed in a second direction. The second direction crosses the lower bit line. A pad electrode is insulated from the lower word line and a sidewall of the trap site and is connected to the lower bit line. A cantilever electrode(50) is positioned in the first direction at an upper part from the trap site in order to form a lower air gap therebetween. The cantilever electrode is connected to the pad electrode and is curved in a third direction in order to be in contact with the trap site by electric field induced from electric charges applied to the lower word line. An upper word line(40) is formed in the second direction and has an upper gap from the upper bit line.

Abstract translation: 提供一种多位机电存储器件及其制造方法，通过形成矩阵型的单元阵列来增加或最大化其积分度。 衬底（10）包括预定的平坦表面。 在基板上沿第一方向形成下位线（20）。 在第二方向上形成下字线（30）和陷阱位置（80）。 第二个方向穿过下位线。 焊盘电极与下字线和陷阱位置的侧壁绝缘，并连接到下位线。 悬臂电极（50）在捕获位置的上部位于第一方向上，以在它们之间形成较低的气隙。 悬臂电极连接到焊盘电极，并且在第三方向上弯曲，以便通过从施加到下字线的电荷引起的电场与陷阱位置接触。 在第二方向上形成上字线（40），并且具有与上位线的上间隙。

公开(公告)号：KR1020080046787A

公开(公告)日：2008-05-28

申请号：KR1020060116198

申请日：2006-11-23

Applicant: 삼성전자주식회사

Inventor： 이성영 ,  김동원 ,  김민상 ,  윤은정 ,  박동건

IPC: H01L21/8247

Abstract: A memory device is provided to easily form write and read wordlines having predetermined voids on and under a bitline in which a switching operation is performed, by removing first and second sacrificial layers surrounding the upper and lower portions of a bitline exposed by a trench. A first wordline with a predetermined thickness is formed in one direction on a substrate(10) with a predetermined flat surface. A second wordline is formed in a direction parallel with the first wordline, floating over the first wordline to have a predetermined void. First and second interlayer dielectrics(80,90) with predetermined heights are formed on the substrate and the lateral surface of the first wordline to float the second wordline, supporting the lateral surface of the second wordline. A bitline(50) is refracted in a vertical direction approximating the first or second wordline in a predetermined condition, passing through the center of the void in the upper part of the first wordline in a position between the first and second interlayer dielectrics and formed in a direction crossing the first wordline. A trap site(30) is stacked on the first wordline under the bitline, trapping predetermined charges to electrostatically fix the bitline refracted to the direction of the first wordline. The trap site can have a stack structure of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer. First and second sacrificial layers can include a polysilicon material.

Abstract translation: 提供一种存储器件，通过去除围绕由沟槽暴露的位线的上部和下部的第一和第二牺牲层，容易地形成在其中进行切换操作的位线上和下方具有预定空隙的写入和读取字线。 具有预定厚度的第一字线在具有预定平坦表面的基板（10）上沿一个方向形成。 在与第一字线平行的方向上形成第二字线，在第一字线上漂浮以具有预定的空隙。 具有预定高度的第一和第二层间电介质（80,90）形成在基板和第一字线的侧表面上，以浮动第二字线，支撑第二字线的侧表面。 位线（50）在与第一或第二字线接近的垂直方向上以预定条件折射，穿过位于第一和第二层间电介质之间的位置的第一字线的上部的空隙的中心，并形成在 横过第一个字线的方向。 陷阱位置（30）堆叠在位线下方的第一字线上，捕获预定电荷以将位线静电固定到第一字线的方向。 陷阱位置可以具有第一氧化硅层，氮化硅层和第二氧化硅层的堆叠结构。 第一和第二牺牲层可以包括多晶硅材料。

公开(公告)号：KR1020080017779A

公开(公告)日：2008-02-27

申请号：KR1020060079407

申请日：2006-08-22

Applicant: 삼성전자주식회사

Inventor： 윤은정 ,  김민상 ,  김성민 ,  김동원 ,  김성환

IPC: H01L27/115

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10876 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7926

Abstract: A non-volatile memory device and a manufacturing method thereof are provided to improve a characteristic of erasing operation by easily eliminating charges accumulated on an oxide-nitride-oxide layer. A first gate insulation layer(118) is formed on both sides of a first gate electrode(120). A pair of channel regions(142) is formed in parallel with a center of the first gate electrode, and vertically extends adjacent to the first gate insulation layer. A pair of first source/drain regions(138) are formed in parallel with a lower portion of the first gate electrode, and a pair of source/drain regions(140) are formed in parallel with an upper portion of the first gate electrode. A second gate electrode(136) is interposed between the first source/drain region and the second source/drain region. The second gate electrode is enclosed by a second gate insulation layer(132).

Abstract translation: 提供了一种非易失性存储器件及其制造方法，通过容易地消除积聚在氧化物 - 氧化物 - 氧化物层上的电荷来提高擦除操作的特性。 第一栅极绝缘层（118）形成在第一栅电极（120）的两侧。 一对沟道区域（142）与第一栅电极的中心平行地形成，并且与第一栅绝缘层相邻地垂直延伸。 与第一栅极的下部平行地形成一对第一源极/漏极区域，并且与第一栅极电极的上部平行地形成一对源极/漏极区域（140）。 第二栅电极（136）介于第一源极/漏极区域和第二源极/漏极区域之间。 第二栅电极由第二栅极绝缘层（132）包围。

公开(公告)号：KR1020080011488A

公开(公告)日：2008-02-05

申请号：KR1020060071875

申请日：2006-07-31

Applicant: 삼성전자주식회사

Inventor： 김민상 ,  이성영 ,  김성민 ,  윤은정 ,  최인혁

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/66636 ,  H01L29/78696

Abstract: A method for fabricating a semiconductor device including a multiple channel MOS transistor is provided to simplify an ion implantation process of a source/drain layer by forming a planarized source/drain layer on the upper surface of a semiconductor device without a facet. A preliminary active pattern(40) is formed on a semiconductor substrate(10) wherein a plurality of gate formation layers and a plurality of single crystal silicon layers are repeatedly stacked in the preliminary active pattern. A hard mask is formed on the preliminary active pattern. By using the hard mask, the preliminary active pattern is etched to the surface of the substrate to form an active channel pattern. A source/drain layer having a flat upper surface is formed in a portion removed in forming the active channel pattern. The plurality of gate formation layers are selectively etched to form a plurality of tunnels. A gate(50) fills the plurality of tunnels, surrounding the active channel pattern and protruding to the upper portion of the active channel pattern. The gate formation layer can be made of germanium or silicon germanium having etch selectivity with respect to the single crystal silicon layer.

Abstract translation: 提供一种用于制造包括多通道MOS晶体管的半导体器件的方法，以通过在半导体器件的上表面上形成平面化的源极/漏极层来简化源极/漏极层的离子注入工艺，而无需刻面。 在半导体衬底（10）上形成初步有源图案（40），其中多个栅极形成层和多个单晶硅层在预活性图案中重复堆叠。 在初步活性图案上形成硬掩模。 通过使用硬掩模，将预活性图案蚀刻到衬底的表面以形成有源沟道图案。 具有平坦的上表面的源极/漏极层形成在形成有源沟道图案中去除的部分中。 多个栅极形成层被选择性地蚀刻以形成多个隧道。 门（50）填充围绕有源通道图案并突出到活动通道图案的上部的多个通道。 栅极形成层可以由具有相对于单晶硅层的蚀刻选择性的锗或硅锗制成。

公开(公告)号：KR100790822B1

公开(公告)日：2008-01-02

申请号：KR1020060074015

申请日：2006-08-07

Applicant: 삼성전자주식회사

Inventor： 이성영 ,  김동원 ,  박현우 ,  윤은정

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/10 ,  H01L2924/0002 ,  H01L27/11568 ,  H01L21/28282 ,  H01L27/2463 ,  H01L2924/00

Abstract: A non-volatile memory device and a method for manufacturing the same are provided to maintain a curved state of a bit line by using trapped electric charges. A plurality of word lines(20) are formed in parallel to each other in a constant interval to one direction. A bit line(50) passes the word lines and is refracted on one direction to the word lines. A trap site(30) is formed in an insulating state between the bit line and the word line adjacent to one side of the bit line. The trap site is formed to trap predetermined charges in order to fix the bit line refracted to one side in an electrostatic manner. One of the word lines is formed on a substrate. A first interlayer dielectric is formed to support the remaining word line on the substrate in order to float the remaining word line in a predetermined gap from one word line.

Abstract translation: 提供了一种非易失性存储器件及其制造方法，通过使用被俘获的电荷来保持位线的弯曲状态。 多个字线（20）以相对于一个方向的恒定间隔彼此平行地形成。 位线（50）通过字线，并且在一个方向上折射到字线。 陷阱位置（30）形成在与位线一侧相邻的位线和字线之间的绝缘状态。 陷阱位置被形成为捕获预定电荷，以便以静电方式将位线折射到一侧。 字线之一形成在基板上。 形成第一层间电介质以支撑衬底上的剩余字线，以便将剩余字线从一个字线浮动在预定间隙中。

公开(公告)号：KR100772935B1

公开(公告)日：2007-11-02

申请号：KR1020060074202

申请日：2006-08-07

Applicant: 삼성전자주식회사

Inventor： 윤은정 ,  이성영 ,  김민상 ,  김성민 ,  조혜진

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7827 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/66666 ,  H01L29/7831 ,  H01L29/7926 ,  H01L21/28282 ,  H01L29/66833

Abstract: A transistor and a manufacturing method thereof are provided to increase an integration level of the transistor by forming a channel region, which is elongated in a vertical direction. A transistor includes a gate electrode(111), an insulation film(109), a gate insulation film(110), a pair of channel regions(117), a pair of first source/drain regions(115), and a pair of second source/drain regions(116). The insulation film is formed on the gate electrode. The gate insulation films are formed at both sidewalls of the gate. The channel regions are parallel to the sidewalls and contacted with the gate insulation film. The channel regions are elongated in a vertical direction. The first source/drain regions are connected to lower portions of the channel regions and elongated in a horizontal direction. The second source/drain regions are connected to upper portions of the channel regions and parallel to the sidewalls of the insulation film. The second source/drain regions are elongated in the horizontal direction.

Abstract translation: 提供晶体管及其制造方法，以通过形成在垂直方向上延伸的沟道区域来增加晶体管的积分电平。 晶体管包括栅电极（111），绝缘膜（109），栅极绝缘膜（110），一对沟道区（117），一对第一源极/漏极区（115）和一对 第二源/漏区（116）。 绝缘膜形成在栅电极上。 栅极绝缘膜形成在栅极的两个侧壁处。 通道区域平行于侧壁并与栅极绝缘膜接触。 通道区域在垂直方向上是细长的。 第一源极/漏极区域连接到沟道区域的下部并在水平方向上延伸。 第二源/漏区连接到沟道区的上部并平行于绝缘膜的侧壁。 第二源极/漏极区域在水平方向上是细长的。

公开(公告)号：KR1020070068725A

公开(公告)日：2007-07-02

申请号：KR1020050130671

申请日：2005-12-27

Applicant: 삼성전자주식회사

Inventor： 김민상 ,  김동원 ,  이성영 ,  김성민 ,  윤은정 ,  최용락

IPC: H01L21/336

Abstract: A method for fabricating a semiconductor device having a CMOS transistor is provided to simplify the process by forming plural thin channels on one active pattern and forming a gate electrode to surround the channels. A first active pattern and a second active pattern are formed in a first region and a second region on a semiconductor substrate. A single crystal silicon layer doped with n-type conductive impurities is formed on a side of the first active pattern and the substrate to form a first source/drain region(23). A single crystal silicon layer doped with p-type conductive impurities is formed on a side of the second active pattern and the substrate to form a second source/drain region(24). Sacrificial layer patterns are selectively etched to form plural first and second tunnels which are buried to form first and second gate electrodes.

Abstract translation: 提供一种用于制造具有CMOS晶体管的半导体器件的方法，以通过在一个有源图案上形成多个薄沟道并且形成围绕通道的栅电极来简化工艺。 第一有源图案和第二有源图案形成在半导体衬底上的第一区域和第二区域中。 在第一有源图案和衬底的一侧上形成掺杂有n型导电杂质的单晶硅层，以形成第一源/漏区（23）。 掺杂有p型导电杂质的单晶硅层形成在第二有源图案和衬底的一侧以形成第二源/漏区（24）。 牺牲层图案被选择性地蚀刻以形成多个第一和第二隧道，这些隧道被埋入以形成第一和第二栅电极。

公开(公告)号：KR100674987B1

公开(公告)日：2007-01-29

申请号：KR1020050072999

申请日：2005-08-09

Applicant: 삼성전자주식회사

Inventor： 윤은정 ,  이성영 ,  김성민 ,  박동건 ,  최동욱

IPC: H01L21/336

Abstract: A method of driving a transistor formed on a bulk wafer substrate is provided to restrain a turn-on state of a parasitic transistor and to prevent the degradation of a device due to the parasitic transistor without a channel separating ion implantation. A reverse body bias is applied to a substrate in order to prevent a turn-on state of a parasitic transistor, wherein the parasitic transistor is formed in the substrate. The substrate includes at least one completely depleted channel region. A bulk wafer substrate is used as the substrate. The completely depleted channel region is a floating channel region.

Abstract translation: 提供一种驱动形成在体晶片衬底上的晶体管的方法，以限制寄生晶体管的导通状态并且防止由于寄生晶体管而导致的器件退化，而没有沟道分离离子注入。 为了防止寄生晶体管的导通状态，向衬底施加反向体偏置，其中寄生晶体管形成在衬底中。 衬底包括至少一个完全耗尽的沟道区。 体晶片衬底被用作衬底。 完全耗尽的沟道区域是浮动沟道区域。

公开(公告)号：KR100618893B1

公开(公告)日：2006-09-01

申请号：KR1020050030947

申请日：2005-04-14

Applicant: 삼성전자주식회사

Inventor： 김성민 ,  김민상 ,  윤은정

IPC: H01L21/335 ,  H01L29/78