公开(公告)号：WO1994023415A1

公开(公告)日：1994-10-13

申请号：PCT/US1994003633

申请日：1994-04-01

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BASSETTI, Chester, Floyd, Jr. ,  CHANG, Chin-Hsian ,  BRIL, Vlad ,  BINDLISH, Rakesh, Kumar

IPC: G09G03/36

CPC classification number: G09G3/2011 ,  G09G3/3644 ,  G09G3/3681 ,  G09G3/3685 ,  G09G3/3692 ,  G09G3/3696 ,  G09G2320/0204 ,  G09G2320/0209 ,  G09G2320/041

Abstract: A method and apparatus for compensating crosstalk in liquid crystal displays (1 and 2) is disclosed which involves applying boost voltages (V5- and V0+) to the rows (40) and columns (38) of the display (1 and 2) in proportion to the number of ON pixels in a row (40) or column (38), the number of transitions between "ON-and-OFF" or "OFF-and-ON" in each column, and the position of the pixel (Px, y) ina row (40). "Boost" voltages (V5- and V0+) are applied to each row (40) as it is being actively scanned to provide horizontal crosstalk compensation, while "boost" voltages (V5- and V0+) are applied to each column (38) during the vertical retrace interval of the display sequence to provide vertical crosstalk compensation. In a preferred embodiment, the vertical crosstalk compensation is determined during the vertical retrace interval over several frames.

Abstract translation: 公开了用于补偿液晶显示器（1和2）中的串扰的方法和装置，其包括以比例向显示器（1和2）的行（40）和列（38）施加升压电压（V5-和V0 +） 相对于行（40）或列（38）中的ON像素的数量，每列中的“ON-OFF”或“OFF-ON”之间的转换次数和像素的位置（Px ，y）行（40）。 当它被主动扫描以提供水平串扰补偿时，将“升压”电压（V5-和V0 +）施加到每一行（40），而在每个列（38）处施加“升压”电压（V5-和V0 +） 显示序列的垂直回扫间隔提供垂直串扰补偿。 在优选实施例中，垂直串扰补偿在几个帧的垂直回扫间隔期间被确定。

公开(公告)号：WO1990012367A1

公开(公告)日：1990-10-18

申请号：PCT/US1990001953

申请日：1990-04-10

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  PATIL, Suhas, S. ,  BASSETTI, Chester, Floyd, Jr. ,  REDDY, Dayakar, Chandrum

IPC: G06F15/00

CPC classification number: G09G3/20 ,  G09G3/3611 ,  G09G2340/0421 ,  G09G2340/0471 ,  G09G2340/0478 ,  G09G2340/0485 ,  G09G2360/04

Abstract: A method for controlling the vertical centering of sequential frames of a raster image on a raster imaging surface, involves detecting the vertical location of the last line of the raster image in the frame preceding the frame to be controlled; and controlling the beginning of the raster image of the controlled frame on the basis of the location of the detected last line (Row Offset Register ROR; Row Segment Total Register RSTR; Row Counter RCtr; Counter NCtr). The invention also provides for automatic centering of the image on the imaging surface, and for compression of the raster image.

Abstract translation: 一种用于控制光栅图像在光栅成像表面上的连续帧的垂直定中心的方法涉及检测在要被控制的帧之前的帧中光栅图像的最后一行的垂直位置; 根据检测到的最后一行（行偏移寄存器ROR;行段总寄存器RSTR;行计数器RCtr;计数器NCtr）的位置来控制受控帧的光栅图像的开始。 本发明还提供了图像在成像表面上的自动对中以及用于光栅图像的压缩。

公开(公告)号：WO1998028714A1

公开(公告)日：1998-07-02

申请号：PCT/US1997023982

申请日：1997-12-19

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  WANG, Vincent, W. ,  SOONG, Jih-Hsien ,  SHU, Hongjun ,  CHAN, Tzoyao

IPC: G06T15/10

CPC classification number: G06F12/0875 ,  G06T15/04 ,  G06T15/10

Abstract: A circuit and method for increasing the processing efficiency of texture map data requests within a 3D subunit of a computer controlled graphics display system. The 3D graphics display subsystem includes a polygon engine, a texture map engine and a pixel pipeline. The texture map engine contains a texture map data access (TDA) circuit having a cache controller with a computer readable cache memory for containing recently used texture maps stored in (u, v) coordinate space. The cache controller is limited in handling only n cache miss operations simultaneously. In one embodiment, n is 1. The TDA circuit also contains a texture map address (TMA) FIFO memory unit for storing texture map addresses associated with texture data requests that hit or missed in the cache memory unit. Since the cache controller handles up to n misses, the texture engine stalls when the (n+1) unprocessed texture request miss is encountered. Therefore, the TMA FIFO at any time contains at most n miss addresses therein. Processing efficiency is increased when a miss is encountered but the TMA FIFO contains unprocessed hit addresses. At this time, simultaneously with the cache controller fetching the texture data for the missed address, it can also advantageously: (1) supply data from the cache memory for the previously encountered and stored hit addresses; and (2) accept new hit addresses into the TMA FIFO thereby effectively avoiding a texture engine stall. This is quite unlike the prior art systems which process no hit addresses upon a texture miss but rather stall the texture engine.

Abstract translation: 一种用于增加计算机控制的图形显示系统的3D子单元内的纹理映射数据请求的处理效率的电路和方法。 3D图形显示子系统包括多边形引擎，纹理映射引擎和像素管道。 纹理映射引擎包含具有高速缓存控制器的纹理映射数据访问（TDA）电路，该高速缓存控制器具有用于包含存储在（u，v）坐标空间中的最近使用的纹理映射的计算机可读高速缓冲存储器。 缓存控制器在仅处理n个缓存未命中操作的同时受到限制。 在一个实施例中，n为1.TDA电路还包含纹理映射地址（TMA）FIFO存储器单元，用于存储与高速缓冲存储器单元中的命中或错过的纹理数据请求相关联的纹理映射地址。 由于缓存控制器处理多达n个未命中，当遇到第（n + 1）个未处理的纹理请求缺失时，纹理引擎停止。 因此，TMA FIFO在任何时候最多包含n个未命中的地址。 当遇到错过但是TMA FIFO包含未处理的命中地址时，处理效率会提高。 此时，与缓存控制器同时获取遗漏地址的纹理数据，还可以有利地：（1）从高速缓冲存储器提供先前遇到和存储的命中地址的数据; 和（2）接受新的命中地址到TMA FIFO，从而有效地避免纹理引擎失速。 这与现有技术的系统完全不同，这种系统在纹理丢失时不处理命中地址，而是阻止纹理引擎。

公开(公告)号：WO1998028713A1

公开(公告)日：1998-07-02

申请号：PCT/US1997022979

申请日：1997-12-19

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  LIN, Ming-Te ,  TSAI, Warren ,  CHAN, Tzoyao

IPC: G06T15/10

CPC classification number: G06T15/04 ,  G06T1/60 ,  G06T11/40

Abstract: Circuits and methods for enhanced caching and pipelining of graphics texture data within a computer controlled graphics display system. The present invention includes: an improved three level texture map memory caching system; a pixel pipeline coupled to the output of a triangle engine for reducing triangle engine stalls, and a tile-in-tile (e.g., tile and subtile) texture map memory management scheme for increasing texture cache hits. These three systems cooperate together to increase graphics throughput within the computer controlled graphics display system. The three level texture map memory caching system includes a first level cache (L1) residing in the texture engine and contains subtiles that are cached in and out on a least recently used (LRU) basis. The second level cache (L2), e.g., in the off-screen RAM, is a larger cache that caches in and out tile length data. The third level cache (L3) resides in the host computer's main memory. In one embodiment, L1 is approximately 2k bytes, L2 is approximately 128k bytes, and main memory is accessible up to 32M bytes. The pixel pipeline coupled to the triangle engine advantageously allows the processing of triangle polygon information (e.g., color) during a texture data fetch interval of the texture engine. Additionally, the tile-in-tile memory addressing system provides a memory management technique that increases the chances of cache memory hits within the texture engine of the present invention by caching specially arraigned tiles and subtiles thereof during texture map data access operations.

Abstract translation: 用于在计算机控制的图形显示系统内增强图形纹理数据的缓存和流水线的电路和方法。 本发明包括：改进的三级纹理贴图存储器缓存系统; 耦合到用于减少三角形引擎停止的三角形引擎的输出的像素流水线，以及用于增加纹理缓存命中的瓦片（例如，瓦片和子屏蔽）纹理图存储器管理方案。 这三个系统协同工作，以增加计算机控制的图形显示系统内的图形吞吐量。 三级纹理贴图存储器缓存系统包括驻留在纹理引擎中的第一级缓存（L1），并且包含在最近最少使用（LRU）的基础上被高速缓存的缓存。 例如在屏幕外RAM中的第二级高速缓存（L2）是高速缓存输入和输出瓦片长度数据的较大缓存。 第三级缓存（L3）位于主机的主存中。 在一个实施例中，L1大约为2k字节，L2为大约128k字节，并且主存储器可访问高达32M字节。 耦合到三角形引擎的像素流线有利地允许在纹理引擎的纹理数据提取间隔期间处理三角形多边形信息（例如，颜色）。 另外，瓦片内存存储器寻址系统提供了一种存储器管理技术，其通过在纹理映射数据访问操作期间缓存特别引人注目的瓦片和其副本来增加本发明的纹理引擎内的高速缓冲存储器命中的机会。

公开(公告)号：WO1998026507A1

公开(公告)日：1998-06-18

申请号：PCT/US1997022475

申请日：1997-12-09

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  CROMAN, Russell

IPC: H03M01/06

CPC classification number: H03M1/0678 ,  H03M1/36

Abstract: A method and circuit for minimizing the differences between members of an array of electrical circuits formed in an integrated circuit is provided. Edge effects seen at the edges of the array are minimized by providing dummy, redundant, or compensation electrical circuits at the edges of the array. These additional electrical circuits are similar to the electrical circuits within the inner portions of the array in both physical layout and electrical operation. In particular, the additional edge electrical structures are made to be electrically operative so that both the physical and electrical environment surrounding the inner array electrical structures is substantially homogeneous throughout the array. In one particular application, an array of comparator circuits for an analog to digital converter of a read channel circuit is provided with additional comparators at the edge of the array. The additional (or dummy) comparators are electrically operative; however, their outputs need not be utilized. The additional (or dummy) comparators improve mismatch characteristics between the utilized comparators in the inner portion of the array.

Abstract translation: 提供了一种用于最小化在集成电路中形成的电路阵列的构件之间的差异的方法和电路。 通过在阵列边缘提供虚拟，冗余或补偿电路来最小化在阵列边缘看到的边缘效应。 在物理布局和电气操作中，这些附加的电路类似于阵列的内部部分内的电路。 特别地，附加的边缘电气结构被制造为电操作的，使得围绕内部阵列电气结构的物理和电气环境在整个阵列中基本上是均匀的。 在一个特定应用中，用于读取通道电路的模数转换器的比较器电路阵列在阵列的边缘处设有附加的比较器。 附加（或虚拟）比较器电气操作; 然而，它们的输出不需要使用。 附加（或虚拟）比较器改善了阵列内部所使用的比较器之间的失配特性。

公开(公告)号：WO1998021647A1

公开(公告)日：1998-05-22

申请号：PCT/US1997020738

申请日：1997-11-14

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  NOOKALA, Narasimha ,  SIVAMANI, Kameswaren ,  SPONRING, Otto

IPC: G06F05/06

CPC classification number: G06F5/06

Abstract: A mechanism to effectively retrieve residual data received from a serial data source is provided. As the shift register receives serial data from the serial data source, the activities and content of the shift register is monitored. Status bits are set to reflect the activities and content. These status bits are used to determine whether the shift register contains residual data and whether such residual data should be ignored the serial data received from the serial data source is output to a destination.

Abstract translation: 提供了一种有效检索从串行数据源接收的残留数据的机制。 当移位寄存器从串行数据源接收串行数据时，监视移位寄存器的活动和内容。 状态位被设置为反映活动和内容。 这些状态位用于确定移位寄存器是否包含残差数据，以及是否忽略这种残留数据，将从串行数据源接收的串行数据输出到目的地。

公开(公告)号：WO1998014932A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017659

申请日：1997-09-30

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  NOOKALA, Narasimha ,  SPONRING, Otto ,  KAMESWAREN, Sivamani

IPC: G09G03/36

CPC classification number: G09G3/3611 ,  G09G3/20 ,  G09G2330/022 ,  G09G2340/0428

Abstract: An arrangement, system, and method to allow a computer system to have a normal operating mode with full display capability and a low-power operating mode with reduced display capability is provided. The computer system automatically switches to the low-power operating mode from the normal operating mode following a programmable period of inactivity. While display data is retrieved from an external DRAM in the normal operating mode, display data is retrieved from an internal SRAM in the low-power operating mode. The computer system switches back to the normal operating mode when one of the predetermined activities is detected.

Abstract translation: 提供一种用于允许计算机系统具有全显示能力的正常操作模式和具有降低的显示能力的低功率操作模式的布置，系统和方法。 计算机系统在可编程的不活动时间段后，从正常操作模式自动切换到低功耗工作模式。 当在正常操作模式下从外部DRAM检索显示数据时，在低功率操作模式下从内部SRAM检索显示数据。 当检测到预定活动之一时，计算机系统切换回正常操作模式。

公开(公告)号：WO1997012363A3

公开(公告)日：1997-04-03

申请号：PCT/US1996015582

申请日：1996-09-26

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZOOK, Christopher, P.

IPC: G11B20/14

公开(公告)号：WO1997008704A1

公开(公告)日：1997-03-06

申请号：PCT/US1996013869

申请日：1996-08-29

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RUNAS, Michael, E.

IPC: G11C11/407

CPC classification number: G11C5/025 ,  G11C5/146 ,  G11C11/4074

Abstract: Substrate bias control circuitry (100) is provided which includes a bias sensor (101) for measuring a bias voltage of a substrate and generating a control signal and response. A master oscillator (102) is provided for generating a first driving signal, a frequency of the first driving signal adjusted by the control signal generated by the bias sensor (101). A first charge pump (103) is provided for pumping electrons into a substrate in response to the first driving signal. A slave oscillator generates a second driving signal, a frequency of the second driving signal is determined from the frequency of the first driving signal using a phase-locked loop. A second charge pump (105) is provided for pumping electrons into the substrate in response to the second driving signal.

Abstract translation: 提供了衬底偏置控制电路（100），其包括用于测量衬底的偏置电压并产生控制信号和响应的偏置传感器（101）。 提供主振荡器（102），用于产生第一驱动信号，通过由偏置传感器（101）产生的控制信号调节的第一驱动信号的频率。 第一电荷泵（103）被提供用于响应于第一驱动信号将电子泵送到衬底中。 从振荡器产生第二驱动信号，使用锁相环从第一驱动信号的频率确定第二驱动信号的频率。 提供第二电荷泵（105），用于响应于第二驱动信号将电子泵送到衬底中。

公开(公告)号：WO1997006523A1

公开(公告)日：1997-02-20

申请号：PCT/US1996012829

申请日：1996-08-05

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RAO, G., R., Mohan

IPC: G09G01/16

CPC classification number: G09G5/399 ,  G09G5/363 ,  G09G2360/122 ,  G09G2360/125

Abstract: A processing system (100) includes a unified memory system (105) having a system memory area (109) and a plurality of frame buffer areas (110/111). A central processing unit (101) has within its address space unified system memory (105) and is operable to update display data in a first selected one from the frame buffer areas (110/111) while display data from a second selected one of the frame buffer areas (110/111) provides data for refresh of a display screen of an associated display device.

Abstract translation: 处理系统（100）包括具有系统存储区域（109）和多个帧缓冲区域（110/111）的统一存储器系统（105）。 中央处理单元（101）在其地址空间内具有统一的系统存储器（105），并且可操作以从帧缓冲器区域（110/111）更新第一选定的显示数据，同时从第二所选择的一个 帧缓冲区（110/111）提供用于刷新相关联的显示设备的显示屏幕的数据。