公开(公告)号：JPS5948368A

公开(公告)日：1984-03-19

申请号：JP15657782

申请日：1982-09-10

Applicant: Hitachi Ltd ,  Hitachi Elevator & Service

Inventor： KUROSAWA KENICHI ,  OKA TAKAAKI ,  YONEDA KENJI ,  UEJIMA TAKAAKI ,  MIURA MASAKI

IPC: B66B1/18 ,  B66B3/00

公开(公告)号：JPS5926872A

公开(公告)日：1984-02-13

申请号：JP13225082

申请日：1982-07-30

Applicant: Hitachi Ltd

Inventor： KUROSAWA KENICHI ,  MIURA MASAKI ,  YONEDA KENJI ,  HIRASAWA KOUTAROU

IPC: B66B1/18 ,  B66B3/00

公开(公告)号：JP2006246280A

公开(公告)日：2006-09-14

申请号：JP2005061786

申请日：2005-03-07

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： KUROSAWA KENICHI

IPC: H04L25/02 ,  H02G3/38 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus for connecting a branch cable capable of reducing reflection noise in a network composed of a differential trunk cable and a plurality of differential branch cables, and to provide the branch cable. SOLUTION: A resistor is built in the apparatus at the side of differential branch cables so as to take impedance matching. Components 201, 202, 20n are branch cable connecting apparatus and incorporate matching resistors 21, 22, 23, 24, 2n, 2n+1. In the network composed of the differential trunk cable and the plurality of differential branch cables, a structure having the branch cable connection apparatus, which is incorporated with a resistor for matching property impedance, and a resistance component at the side of branch cable connection for reducing the reflection noise reduction. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决的问题：提供一种用于连接能够减少由差分中继电缆和多个差分分支电缆组成的网络中的反射噪声的分支电缆的装置，并提供分支电缆。

解决方案：在差分分支电缆一侧的设备中内置一个电阻器，以获得阻抗匹配。 部件201,202,20n是分支电缆连接装置，并且包括匹配电阻器21,22,23,24,2n，2n + 1。 在由差分干线电缆和多条差分分支电缆组成的网络中，具有分支电缆连接装置的结构，其具有用于匹配特性阻抗的电阻器，以及用于减少分支电缆连接侧的电阻部件 反射降噪。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2003186507A

公开(公告)日：2003-07-04

申请号：JP2001384200

申请日：2001-12-18

Applicant: HITACHI LTD

Inventor： NAGAHAMA NOBUKI ,  KUROSAWA KENICHI

IPC: G05B9/02 ,  G05B19/05

Abstract: PROBLEM TO BE SOLVED: To provide a distributed control system, capable of reducing the cost of the system without stopping control of the whole system, even when a controller is under fault conditions. SOLUTION: The system connects a programing device 101 of a ladder sequence and a plurality of control devices 102 to a data transmission path 103, capable of communicating control data among each device, where the programing device 101 divides the described ladder sequence at each portion related to each control device for adding proper block IDs and adds data IDs to the control data of each control device and distributes the ladder sequence divided and added the proper block IDs and the control data over a plurality of control devices; therefore, each control device can be automatically operated, even if any one of the control devices suffers failures. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001092714A

公开(公告)日：2001-04-06

申请号：JP26498599

申请日：1999-09-20

Applicant: HITACHI LTD

Inventor： OGURA MAKOTO ,  KUROSAWA KENICHI ,  TAKEWA HIDEHITO ,  ISHIKURA HIDEJI ,  ARITA YUTAKA ,  YAMAMOTO MASAYUKI

IPC: G06F12/06 ,  G06F12/00 ,  G06F12/04 ,  G06F13/16

Abstract: PROBLEM TO BE SOLVED: To prevent the number of pins for a memory controller from being increased even though the capacity of a FlashROM is increased in the memory controller controlling a SDRAM and the FlashROM. SOLUTION: This memory controller is provided with control logic which defines data signal lines connected to SDRAMs 2 and 3 as an address data bus that is also used as the address of a FlashROM 6, and which controls the address data but that is used for both the data signal of the SDRAMs and the address signal of the FlashROM in the memory controller so that the address signal of the FlashROM is outputted to the bus when accessing the FlashROM and the data signal is outputted when accessing the SDRAMs. Thus, it is possible to expand the address of the FlashROM without increasing the number of pins for the memory controller.

公开(公告)号：JP2000152497A

公开(公告)日：2000-05-30

申请号：JP33015298

申请日：1998-11-05

Applicant: HITACHI LTD

Inventor： KAMINAGA YASUO ,  MORIOKA MICHIO ,  KUROSAWA KENICHI ,  ISHIKURA HIDEJI ,  MATSUDA KOJI

IPC: H02J1/00

Abstract: PROBLEM TO BE SOLVED: To contrive the protection of breakdown strength of a group of LSIs in a system, and protect the LSIs from breakage, by putting the device in such circuit constitution that is keeps the potential difference between heterogeneous power sources especially at power break of a heterogeneous power-source mixed system at a roughly constant low potential difference. SOLUTION: The power sequence circuit of a heterogeneous power system, which applies a plurality of power sources to a group of LSIs or breaks them, has each voltage regulator 2 and 3 which generates a superordinate power source VCC2 and a subordinate power source VCC3 from the highest-order power source VCC1, and power source level detectors 13 and 14 which receives the input of the voltage of the superordinate power source line or the highest- order power source line. Then, a MOS switch 5, a current limiting resistor 8, and a diode 13 are connected in series between the superordinate power source line and the subordinate power source line, and a MOS switch 6, a resistor 10 for charge currents, and an earth terminal are connected in series to the superordinate power source line, and the ON-OFF control of each MOS switch is performed, using the detection signal of each power level detector, and each power voltage is discharged in parallel.

公开(公告)号：JPH11329639A

公开(公告)日：1999-11-30

申请号：JP14079198

申请日：1998-05-22

Applicant: HITACHI LTD

Inventor： MATSUDA KOJI ,  KUROSAWA KENICHI ,  ISHIKURA HIDEJI ,  SHIRATO TAKESHI

IPC: G06F1/18 ,  H01R23/68

Abstract: PROBLEM TO BE SOLVED: To realize size reduction and manufacturing man-hour reduction, by dividing both a substrate having only surface-mounted components related to CPU functions and to communication functions and a substrate having only insert-mount components, into circuits for communication functions and insertion- type connectors for communication of an insert-mounted component substrate, and connecting them by means of connectors for surface-mount and insertion each having a selective impedance matching means for every signal line. SOLUTION: A substrate 101 having only inserted components is loaded with an insertion connector 102 for communication and an insertion connector 110 for power reception. Insertion connectors 104, 103 are connected to surface- mount connectors 106, 107 on a substrate 105 having only CPU functions and surface-mount components, and power feeding and delivery of communication control/data signals are performed. Impedance matching resistors are added to the insertion connectors 104, 103, whereby the waveform of a received signal from the connector 102 for communication is prevented from being disturbed by reflection from the connector. The size of the substrates is reduced and the substrate 101 having only inserted components is manufactured only by an insertion process.

公开(公告)号：JPH11143587A

公开(公告)日：1999-05-28

申请号：JP30526097

申请日：1997-11-07

Applicant: HITACHI LTD

Inventor： KAMINAGA YASUO ,  KUROSAWA KENICHI ,  YAMADA TSUTOMU ,  ARITA YUTAKA ,  MASUI KOJI

IPC: G06F1/26 ,  G06F1/30

Abstract: PROBLEM TO BE SOLVED: To evade generation of a general reset signal and to surely finish a CPU processing when the power supply is interrupted or cut off by monitoring a power cut-off previous announcement signal after reception of a manual or soft reset request signal. SOLUTION: When a power supplied from a power unit 2 is cut off, a reset circuit 19 transmits a manual or soft reset request signal M/S-GR-N to a CPU 31, an ASIC 33 and a communication controller 34 which need a general reset signal GR-N respectively via the logic circuits 15 and 16 and a pulse generation circuit 17. Even when the signal M/S-GR-N is generated right before the power supply is interrupted or cut off, the circuit 15 of the circuit 19 refers to a power cut-off previous announcement signal POP (or a power supply valid signal) to generate the signal GN-R. In such a circuit system, a CPU processing can be finished with no disturbance when the power supply is interrupted or cut off. Thus, emergency information is always protected.

公开(公告)号：JPH10207855A

公开(公告)日：1998-08-07

申请号：JP653897

申请日：1997-01-17

Applicant: HITACHI LTD

Inventor： SAITO MASAHIKO ,  TAKEWA HIDEHITO ,  KUROSAWA KENICHI ,  MIYAZAKI YOSHIHIRO ,  KANEKO SHIGENORI

IPC: G06F11/20 ,  G06F11/16 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To structure the multiple system which can succeed fast in case of a fault by using a shared disk. SOLUTION: A master system computer 100 and a slave system computer send an existence information signal periodically to each other through a supervise processor(SVP) 115. When there is no existence information signal from the master system computer 100 for a certain period, the slave system computer 101 inquires the state of the master system computer 100, and resets the master system computer 100 once through the SVP 115 in case of a transitory fault and takes over its process. In case of a permanent fault, the SVP 115 is made to reset the master system computer 100 continuously, and MOS switches 150 to 153 of a shared disk drive 102 are controlled to electrically disconnect the master system computer 101 from SCSI, thereby taking over the process of the master system computer 101.

公开(公告)号：JPH10126425A

公开(公告)日：1998-05-15

申请号：JP27931596

申请日：1996-10-22

Applicant: HITACHI LTD

Inventor： KAMINAGA YASUO ,  KUROSAWA KENICHI ,  YAMADA TSUTOMU ,  MASUI KOJI ,  OHASHI AKIHIRO

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  H04L12/40

Abstract: PROBLEM TO BE SOLVED: To reduce reflection noise at a bus branchpoint by adjusting the connection point of a main bus and variable impedance to the proceeding direction of a passing signal, changing the impedance value of the variable impedance and matching impedance at the connection point. SOLUTION: The drain-source of an N channel MOS transistor 25 of a bus interface 2 is inserted between a stub bus 21 and a main bus 1. An impedance control circuit 26 adjusts an impedance value between a drain and a source by controlling gate voltage of the transistor 25. That is, the circuit 26 matches impedance at a connection point of a main bus 1 and the transistor 25 by controlling the gate voltage of the transistor 25 and adjusting the impedance value of between a drain and a source.