公开(公告)号：CA2286364A1

公开(公告)日：1998-10-22

申请号：CA2286364

申请日：1998-04-03

Applicant: IBM

Inventor： DODSON JOHN STEVEN ,  KAISER JOHN MICHAEL ,  LEWIS JERRY DON ,  ARIMILLI RAVI KUMAR

IPC: G06F12/08 ,  G06F12/0831

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, a given one of the caches transmits a response indicating that the given cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.