-
公开(公告)号：EP0700004A3
公开(公告)日：1998-07-01
申请号：EP95480104
申请日：1995-08-08
Applicant: IBM
IPC: G06F12/10 , G06F13/36 , G06F15/16 , G06F15/173 , G06F15/177 , G06F13/42
CPC classification number: G06F13/36
Abstract: A method and system are provided for communicating between devices. A signal is output from a first device. In response to the signal, at least one action is initiated by a second device. An indication is output of whether the second device completed the action and of whether operation of the second device is independent of the first device reoutputting the signal.
-
公开(公告)号：JPH10301840A
公开(公告)日：1998-11-13
申请号：JP8892398
申请日：1998-04-01
Applicant: IBM
Abstract: PROBLEM TO BE SOLVED: To transfer data between a power PC processor and an input/output device even when respective little endian byte orders are different by providing the power PC processor, the input/output device and a memory controller for transmitting the data between both of them. SOLUTION: This system is provided with a CPU 710 for using a power PC little endian byte order, an I/O adapter 718 for using a true little endian byte order and a memory controller sub system 501 for communicating the data between the CPU 710 and the I/O adapter 718. The memory controller sub system 501 converts the data transferred from the I/O adapter 718 to the CPU 710 or a memory 714 from the true one to the power PC little endian byte order. The data transferred from the CPU 710 or the memory 114 to the I/O adapter 718 are converted from the power PC one to the true little endian byte order.
-
公开(公告)号：JPH04230555A
公开(公告)日：1992-08-19
申请号：JP24830291
申请日：1991-09-02
Applicant: IBM
Inventor： KAISER JOHN MICHAEL , YOUNGBLOOD LOYAL DAVID
IPC: G06F15/163 , G06F13/00 , G06F13/14 , G06F15/173 , H04L12/00
Abstract: PURPOSE: To provide the distribution control of a port connected to a switch and technique for providing communication with the switch in order to effectively adjust the mutual connection of the port to a cross point switch in terms of a cost. CONSTITUTION: A communication network respectively adds the plural ports which are respectively connected to at least one of data processing system elements 14, 16, 18, 20, 22, 24, 26 and 28. The ports are mutually connected by an information bus. Moreover, the ports are connected to a matrix switch 40 having ability to directly provide a communication channel between the two optional ports of them. Respective ports execute communication with another port with the bus and a control circuit for executing adjustment to permit the matrix switch to directly provide the communication channel between the two ports is added.
-
公开(公告)号：JPH10333985A
公开(公告)日：1998-12-18
申请号：JP9183998
申请日：1998-04-03
Applicant: IBM
Inventor： RAVI KUMAR ARIMIRI , DODSON JOHN STEVEN , KAISER JOHN MICHAEL , JERRY DON LEWIS
IPC: G06F15/16 , G06F12/08 , G06F15/177 , G06F15/163
Abstract: PROBLEM TO BE SOLVED: To permit an efficient intervention of data in a shared state by making the intervention possible as an additional processing when two or more caches keep related data in shared state. SOLUTION: A cache coherency protocol is provided with the five states of latest reference R, modification M, exclusion E, sharing S and invalidation I. Then, a processor for accessing a data value detects the transfer of display and the data are supplied from the cache provided with the copy of the latest reference R. The cache provided with the copy of the latest reference R changes the display and turns it to the display of sharing S at the time of supplying the data and the processor which accesses the data is turned to the display of the latest reference R thereafter. Also, in the case that the processor intends to write the data value, the cache provided with the copy of the latest reference R first is turned to the display of the invalidation I. Thus, by supplying the intervention to the shared data, memory waiting time is largely improved.
-
公开(公告)号：JPH10289157A
公开(公告)日：1998-10-27
申请号：JP7873798
申请日：1998-03-26
Applicant: IBM
Inventor： ARIMILLI RAVI KUMAR , DODSON JOHN STEVEN , KAISER JOHN MICHAEL , LEWIS JERRY DON
IPC: G06F15/16 , G06F12/08 , G06F15/177 , G06F15/163
Abstract: PROBLEM TO BE SOLVED: To execute a reading type operation in a multiprocessor computer system and to improve the memory waiting time by making a requester processor issue a message trying to read the value out of a memory address to a bus and then making every cache snoop the bus to detect the message to give an answer. SOLUTION: A requester processor issues a message to a general-purpose mutual connection part to show that the processor tries to read the value from an address of a memory device. Then every cache snoops the general-purpose mutual connection part to detect the message and transfers an answer to the message. Thereby, a sharing/intervention answer is transferred to show that a cache including the unchanged value corresponding to the address of the memory device can supply the value. The priority is assigned to the answer received from every cache, and each answer and its relative priority are detected. Then the answer having the highest priority is transferred to the requester processor.
-
Patent Agency Ranking6.发明专利
公开(公告)号：JPH10289156A
公开(公告)日：1998-10-27
申请号：JP7872198
申请日：1998-03-26
Applicant: IBM
Inventor： RAVI KUMER ARIMIRI , JOHN STEPHEN DODDSON , KAISER JOHN MICHAEL , JERRY DON LEWIS
IPC: G06F15/16 , G06F12/08 , G06F15/163
Abstract: PROBLEM TO BE SOLVED: To improve the memory waiting time related to a reading type operation by making a requester processor issue a message to try to read an unchanged copy of the value that is latest read and then making a specific cache transfer an answer to show that it can supply the value. SOLUTION: The value are loaded to plural caches from the addresses of a memory device, and a specific cache including an unchanged copy of the value that is latest read is identified among those caches and marked. At the same time, other caches including the unchanged sharing copies are also copied. Then a requester processor issues a message to try to read those value from the addresses of the memory device, and the specific cache transfers an answer to show that it can supply these value. Under such conditions, a protocol including the R which designates a block that is latest read is used in addition to the changing, exclusive, shared and invalid states in order to confirm the cache that owns the unchanged value.
-
公开(公告)号：JPH07112200B2
公开(公告)日：1995-11-29
申请号：JP25296191
申请日：1991-09-04
Applicant: IBM
Inventor： KAISER JOHN MICHAEL , ST CLAIR JOE CHRISTOPHER
IPC: G06F15/163 , G06F13/14 , G06F13/38 , H04Q3/52 , H04L12/40
-
公开(公告)号：JPH10340212A
公开(公告)日：1998-12-22
申请号：JP9145898
申请日：1998-04-03
Applicant: IBM
Inventor： KAISER JOHN MICHAEL , WARREN EDWARD MALE
Abstract: PROBLEM TO BE SOLVED: To make separable failure on a clock synchronous bus, by receiving an input to a shift register and shifting the contents of the shift register when detecting the driver of a data bus in the case of a bus error. SOLUTION: One bus driver and at least two devices are connected to each other and when a failure on the bus, which operates according to a bus clock 130, is separated, an input including a clock input 160 to an N-bit shift register 10 and a driver-enable signal 102 is received, and only when the clock input 160 is positive, the contents of the shift register 100 are shifted. A register 100 is latched corresponding to a detected error and the latched register 100 is scanned. Here, the clock input 160 further includes a system clock signal 130 and a check stop signal 140 and once the check stop signal 140 is received, the shift register clock 150 is stopped.
-
公开(公告)号：JPH10289197A
公开(公告)日：1998-10-27
申请号：JP9034698
申请日：1998-04-02
Applicant: IBM
Inventor： ARIMILLI BABA , KAISER JOHN MICHAEL , KIM KYONGMEE L , MAULE WARREN EDWARD
IPC: G06F13/36 , G06F12/08 , G06F12/0879
Abstract: PROBLEM TO BE SOLVED: To attain the burst transfer of processor data to an I/O device by performing the intermediate cache emulation logic to snatch and process the processor commands requesting the communication with the I/O device. SOLUTION: The processors 10a to 10c control the accesses to a system memory card 46 and an I/O mezzanine bus 36 for a memory/I/O bus controller 30. The bus 36 is connected to one or more I/O bridges 40 via the data links 38a and 38b. The bridges 40 snatch the trigger commands, and the processors 10a to 10c request the communication with an I/O device 60. The I/O bridges 40a and 40b perform the intermediate cache emulation logic to attain the emulation type cache burst transfer of data to the device 60 via an I/O bus 50.
-
公开(公告)号：JPH10289155A
公开(公告)日：1998-10-27
申请号：JP7870898
申请日：1998-03-26
Applicant: IBM
Inventor： RAVI KUMER ARIMIRI , JOHN STEPHEN DODDSON , KAISER JOHN MICHAEL , JERRY DON LEWIS
IPC: G06F15/16 , G06F12/08 , G06F15/163
Abstract: PROBLEM TO BE SOLVED: To improve the memory waiting time related to a reading type operation by making a requester processor issue the messages to try to read the unchanged sharing copies of value of the 1st and 2nd caches and then making one of caches transfer an answer to show that it can supply those cache value. SOLUTION: The value are loaded to at least 1st and 2nd caches from the addresses of a memory device, and the marks are added to both caches to show that they include the unchanged sharing copies of the value. Then a requester processor issues a message to show to try to read these value from the addresses of the memory device, and one of both caches transfers an answer to show that it can supply the value. Under such conditions, a protocol including the R which designates a block that is latest referred to is used in addition to the changing, exclusive, shared and invalid states in order to confirm the cache that owns the unchanged value.
-
-
-
-
-
-
-
-
-
Search Results
48
records
(took 0.02 seconds)
