公开(公告)号：DE102004046806B4

公开(公告)日：2009-07-09

申请号：DE102004046806

申请日：2004-09-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAYERER REINHOLD ,  THOBEN MARKUS

IPC: H01L25/07 ,  H01L23/488

Abstract: A power semiconductor module (1) has power semiconductor components (2, 4, 6, 8, 10, 12) arranged on a substrate (14), at least one portion of which components is connected in parallel and arranged symmetrically on the substrate (14). A second conduction plane (24, 26) is provided for making contact with the power semiconductor components (2, 4, 6, 8, 10, 12). The second conduction plane is arranged in a manner electrically insulated from the substrate surface (16) above the surfaces of the power semiconductor components (2, 4, 6, 8, 10, 12) that are remote from the substrate surface (16).

公开(公告)号：DE102006001874A1

公开(公告)日：2007-07-19

申请号：DE102006001874

申请日：2006-01-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAYERER REINHOLD ,  THOBEN MARKUS

IPC: G01R19/32 ,  G01R31/26 ,  H01L23/58

Abstract: The method involves respectively detecting current and temperature levels by sensor components of a power electronic circuit. The sensor components are selected in such a manner that their voltage-current-temperature characteristics are linearly independent from each other. A calibration of the measured levels takes place with different temperatures and current values by a calibration process. The measured levels are evaluated with parameters determined during the calibration process by an evaluation algorithm for compensating temperature and current dependence of an actual measured value. An independent claim is also included for a measuring device for current and temperature measurement in a power electronic circuit.

公开(公告)号：DE102005007373A1

公开(公告)日：2006-08-24

申请号：DE102005007373

申请日：2005-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAYERER REINHOLD ,  THOBEN MARKUS

IPC: H01L25/07 ,  H01L23/34 ,  H01L23/48

Abstract: A semiconductor assembly is disclosed. One embodiment provides a first semiconductor and a second semiconductor, each having a first main connection and a second main connection arranged on opposite sides, and a carrier having a patterned metallization with a first section spaced apart from a second section. The first semiconductor is electrically connected to the first section by its second main connection, and the second semiconductor electrically connected to the second section by its second main connection. The first semiconductor chip first main connection and the second semiconductor chip first main connection are electrically connected to one another and for the connection of an external load or of an external supply voltage.