公开(公告)号：DE10139827A1

公开(公告)日：2003-03-13

申请号：DE10139827

申请日：2001-08-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  SCHLOESSER TILL

IPC: H01L27/108 ,  H01L21/8242

Abstract: The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.

公开(公告)号：DE10138981A1

公开(公告)日：2003-03-06

申请号：DE10138981

申请日：2001-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS

IPC: H01L21/3063 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242

Abstract: In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a silicon surface region, self-limited oxide formation takes place. The end of this formation is reached as a function of the process parameters such as the doping of the silicon region, the applied voltage and the composition of the electrolyte used, as soon as either a predetermined maximum layer thickness of the formed oxide or a predetermined minimum residual silicon layer thickness between two adjacent recesses is reached. The self-limiting is achieved either as a result of the overall voltage applied over the silicon oxide layer, which has already formed, dropping or as a result of the space charge regions of adjacent recesses coming into contact with one another.

公开(公告)号：DE10136716A1

公开(公告)日：2003-02-13

申请号：DE10136716

申请日：2001-07-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  SCHLOESSER TILL

IPC: H01L25/065 ,  H01L27/108 ,  H01L23/50

Abstract: The manufacturing method uses semiconductor technology for provision of at least one capacitor and transistor for a memory cell of a memory cell field (31), together with a control and evaluation circuit (21), positioned vertically above the memory cells of the memory cell field. The memory cell field and the control and evaluation circuit are incorporated in respective overlapping surface regions (2,3) which are at least partially coupled together. An Independent claim for a dynamic random-access memory element is also included.

公开(公告)号：DE10120053A1

公开(公告)日：2002-11-14

申请号：DE10120053

申请日：2001-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  SELL BERNHARD ,  SAENGER ANNETTE

IPC: H01L21/8242 ,  H01L27/108

Abstract: The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

公开(公告)号：DE10103524A1

公开(公告)日：2002-08-22

申请号：DE10103524

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS

IPC: H01L21/3065 ,  H01L21/033 ,  H01L21/302 ,  H01L21/308 ,  H01L21/311

Abstract: To increase the etching resistance and to reduce the etching rate of a silicon-containing mask layer, an additional substance is mixed into the mask layer or into an etching gas. The additional substance is present in the mask layer or a concentration of the additional substance can be subsequently increased in the mask layer. During a subsequent etching process for patterning using the mask layer, the mask layer is removed at a reduced etching rate.