公开(公告)号：WO03028093A3

公开(公告)日：2003-08-14

申请号：PCT/DE0203023

申请日：2002-08-19

Applicant: INFINEON TECHNOLOGIES AG ,  BIRNER ALBERT ,  BREUER STEFFEN ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  SCHUMANN DIRK

Inventor： BIRNER ALBERT ,  BREUER STEFFEN ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

Abstract: The invention relates to a method for the generation of a Silicon-On-Insulator layer structure on a silicon surface with any shape, whereby the Silicon-On-Insulator structure can only be produced locally. The method comprises the formation of mesopores (10) in the silicon surface region (3), the oxidation of the mesopore surface to give silicon oxide and web regions (22) of single-crystal silicon, remaining between adjacent mesopores (10), whereby said step is terminated as soon as a given minimum silicon wall strength for the web regions (22) is achieved, the release of the web regions (22) between adjacent mesopores at the end away from the semiconductor substrate (2) is carried out and a selective epitaxial process by means of which silicon is selectively grown on the released web regions (22) relative to the silicon oxide regions (11). The method can be used for the production of a vertical transistor and a memory cell with such a selection transistor.

Abstract translation: 本发明涉及一种用于在与该硅 - 绝缘体结构也可本地产生的任何几何形状的硅表面上制作绝缘层结构的硅的方法。 该方法包括：在硅表面面积（3），中孔表面的氧化，以形成单晶硅，其保持（10）相邻的中孔之间的氧化硅和陆地区域（22）中孔（10）的形成，所述步骤 将立即终止陆块区的一个预定的最小硅的壁厚（22）达到，相对的端部暴露于半导体衬底（2）的布置陆地区域相邻的孔（22）之间; 并通过硅到暴露的陆地区域（22）（11）执行选择性外延工艺，对氧化硅的选择性区域长大。 该方法可被用于制造垂直晶体管和具有这样的选择晶体管的存储单元。

公开(公告)号：WO03028104A3

公开(公告)日：2003-08-14

申请号：PCT/DE0202980

申请日：2002-08-14

Applicant: INFINEON TECHNOLOGIES AG ,  LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

Inventor： LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10891

Abstract: A trench capacitor (30) is arranged in a first trench (25) for production of a semiconductor memory (5). A first longitudinal trench (55) is arranged in the substrate (15) next to the first trench (25) and parallel thereto on the other side of the first trench (25), a second longitudinal trench (60) is arranged therein. A first spacer word line (70) is arranged in the first longitudinal trench (55) and a second spacer word line (75) is arranged in the second longitudinal trench (60). Connecting webs (80) are arranged in the first trench (25) between the first spacer word line (70) and the second spacer word line (75) with a thickness (110), which is smaller in the direction of the first spacer word line (70) than half the width of the first trench (25) in the direction of the first spacer word line (70).

Abstract translation: 为了制造半导体存储器（5），沟槽电容器（30）被布置在第一沟槽（25）中。 除了所述第一沟槽（25），第一纵向沟槽（55）和上第一沟槽并行（25），在所述基板的第二纵向沟槽（60）的另一侧（15）被布置。 在第一纵向沟槽（55）中设置第一间隔字线（70），在第二纵向沟槽（60）中设置第二间隔字线（75）。 在所述第一沟槽（25）的连接板（80）设置在所述第一间隔物的字线（70）和具有厚度（110）所述第二间隔的字线（75）（在第一间隔的字线70的方向之间 ）小于第一沟槽（25）朝向第一间隔字线（70）的宽度的一半。

公开(公告)号：WO0211200A8

公开(公告)日：2002-04-11

申请号：PCT/DE0102798

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL BERND ,  LUETZEN JOERN ,  POPP MARTIN ,  SEIDL HARALD

Inventor： GOEBEL BERND ,  LUETZEN JOERN ,  POPP MARTIN ,  SEIDL HARALD

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864

Abstract: The invention relates to a semiconductor memory cell arrangement comprising dynamic memory cells (10) which each have a trench capacitor (1) and a vertical selection transistor (2). Said vertical selection transistor (2) is situated essentially above the trench capacitor (1) and has a series of layers which is offset from the inner electrode of the trench capacitor (1) and which is connected to said inner electrode (11) of the trench capacitor (1). An active intermediate layer (22) is completely surrounded by an insulator layer (24) and a gate electrode layer (25) which is connected to a word line (7). The dynamic memory cells (10) are arranged in the form of a matrix, the trench capacitors (1) and the corresponding vertical selection transistors (2) of the dynamic memory cells (10) succeeding each other in a line and/or column sequence, respectively.

Abstract translation: 具有动态存储单元的半导体存储器单元阵列（10），每一个都具有严重的电容器（1）和一个verikalen选择晶体管（2），其特征在于，垂直选择晶体管（2）基本上高于WOM严重电容器（1）被布置和相对的内部电极 被严重电容器（1）与一个布置成与严重电容器（1），其特征在于，有源中间层（22）被封闭具有完全的绝缘体层（24）和栅电极层（25）的内电极（11）偏移的层序列 Worleitung（7）连接，其中，所述动态存储单元（10）被布置成矩阵，和坟墓电容器（1）和相关联的垂直选择Transistore（2）的动态存储器单元（10），每行和/或列状连续的。

公开(公告)号：WO03081666A8

公开(公告)日：2005-05-12

申请号：PCT/EP0301139

申请日：2003-02-05

Applicant: INFINEON TECHNOLOGIES AG ,  LUETZEN JOERN ,  POPP MARTIN ,  SCHLOESSER TILL

Inventor： LUETZEN JOERN ,  POPP MARTIN ,  SCHLOESSER TILL

IPC: H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10888 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/76897

Abstract: The invention relates to a production method for a contact in a semiconductor structure comprising a substrate (1) provided with a first and second structural element (GS1, GS2) of approximately the same height which are disposed on the surface of the substrate and which are distanced from each other by means of an intermediate space having a critical lateral dimension. The inventive method comprises the following steps: provision of an active area (60) in the substrate (1) between the structural elements (GS1, GS2); raising the active area (60) by selective epitaxy of conductive substrate material (80); and formation of the contact (CB) on the raised active area. The invention also relates to a corresponding contact.

Abstract translation: 本发明提供在半导体结构中的接触包括具有第一和第二在设置于基材表面大约等于高的结构元件（GS1，GS2），基板（1）的制造方法，其彼此通过用临界的横向尺寸的间隙 被间隔开，其包括以下步骤：在所述的结构元件（GS1，GS2）之间的基板（1）提供的有源区（60）; 有源区（60）由导电性衬底材料的选择性生长（80）的增加; 以及形成在凸起有源区的接触（CB）。 本发明还提供了相应的接触。

公开(公告)号：WO02056369A3

公开(公告)日：2003-03-20

申请号：PCT/EP0200102

申请日：2002-01-08

Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  ORTH ANDREAS ,  LUETZEN JOERN

Inventor： GOLDBACH MATTHIAS ,  ORTH ANDREAS ,  LUETZEN JOERN

IPC: H01L27/108 ,  H01L21/20 ,  H01L21/8242

CPC classification number: H01L27/10867 ,  H01L27/1087

Abstract: A method for the production of trench capacitors, especially memory cells and at least one selection transistor for integrated semiconductor memories. According to the invention, the trench for the trench capacitor has a lower trench area (3-10c) in which the capacitor is arranged and an upper trench area (3-10a) in which an electrically conducting connection (3-44, 3-20b) between an electrode of the capacitor (3-20a) to a diffusion area of the selection transistor is disposed. The inventive method reduces the number of process steps for the production of memory cells and enables the production of buried shrouds in the memory capacitors which exhibit the same insulation quality as that which is required for the production of highly integrated memory cells (diameter

Abstract translation: 一种用于严重电容器，尤其是存储单元和用于集成半导体存储器中的至少一个选择晶体管的制备方法进行说明，其中所述沟槽为严重容量下部严重区域（3-10C），其中，所述电容器被布置和上严重区域（3-10C ），其中通过所述电容器（3-20a）的电极的导电性连接（3-44，3-20b）被布置以形成选择晶体管的扩散区域，其包括 这种方法减少了对存储单元的制造工艺步骤的数量，并且使生产掩埋套环在具有绝缘质量的存储电容器，作为用于生产（<300nm的严重直径）是必需的高度集成的存储器单元。

公开(公告)号：WO2004031439A3

公开(公告)日：2004-11-04

申请号：PCT/DE0303188

申请日：2003-09-24

Applicant: INFINEON TECHNOLOGIES AG ,  HECHT THOMAS ,  LUETZEN JOERN

Inventor： HECHT THOMAS ,  LUETZEN JOERN

IPC: C23C16/44 ,  C23C16/455

CPC classification number: C23C16/4412 ,  C23C16/45544 ,  C23C16/45557

Abstract: A sequential gas phase deposition (ALD, atomic layer deposition) of two or more precursors, introduced by means of process gases is controlled in a process chamber (10) of a process reactor (1), whereby the process chamber (10) is connected to an auxiliary chamber (20) for a precursor change and the precursor to be removed is thus diluted in the process chamber (10), such that a process duration in the sequential gas phase deposition, as determined by a precursor exchange, is shortened.

公开(公告)号：WO03017342A2

公开(公告)日：2003-02-27

申请号：PCT/DE0202651

申请日：2002-07-18

Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  HECHT THOMAS ,  LUETZEN JOERN ,  SELL BERNHARD

Inventor： GOLDBACH MATTHIAS ,  HECHT THOMAS ,  LUETZEN JOERN ,  SELL BERNHARD

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L27/10867 ,  H01L21/0274

Abstract: A structure on a layer surface of the semiconductor wafer comprises at least one first surface (8,9) area reflecting electromagnetic radiation and at least one second substantially non-reflecting surface area (10,11,12). A transparent insulating layer (13) and a light-sensitive layer are produced on said layer surface. Electromagnetic radiation is directed at the light-sensitive layer at an incident angle &thetas; and the structure of the layer surface is imaged onto the light-sensitive layer with a lateral replacement.

Abstract translation: 在半导体晶片的表面层的结构具有至少一个反射电磁辐射的第一区域（8,9）和至少一个第二基本上非反射区域的区域（10,11,12）。 在该表面层的透明绝缘层（13）和一光敏层被产生。 的电磁辐射是在入射角θ驱动＆; 引导到感光层，并准备在层表面的结构与在感光层中的横向更换。

公开(公告)号：WO03010826A2

公开(公告)日：2003-02-06

申请号：PCT/EP0207593

申请日：2002-07-08

Applicant: INFINEON TECHNOLOGIES AG ,  BIRNER ALBERT ,  LUETZEN JOERN

Inventor： BIRNER ALBERT ,  LUETZEN JOERN

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/00

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10876 ,  H01L29/66666

Abstract: In order to produce a vertical transistor, a trench (4) is provided whose lateral wall (6) is formed by a monocrystalline semiconductor substrate (2) and whose bottom (8) is formed by a polycrystalline semiconductor substrate (10). A transition region (12) made of an insulating material is placed between the lateral wall (6) and the bottom (8). A semiconductor layer is deposited selective to the material of the transition region (12) whereby enabling an epitaxial semiconductor layer (24) to grow on the lateral wall (6) and a semiconductor layer (26) to grow on the bottom (8), whereby these a space remains between these layers. The deposited semiconductor layers (24, 26) are covered with a thin dielectric (28) that only partially limits a current flow, and the space is filled with a conductive material (30). During a subsequent thermal treatment, dopants diffuse out of the conductive material (30) and into the epitaxial semiconductor layer (26) and form a dopant region (44) therein. The thin dielectric (28) limits the diffusion of the dopants into the semiconductor substrate (2) and prevents the spreading of crystal lattice faults into the epitaxial semiconductor layer (26).

Abstract translation: 用于制造垂直晶体管，沟槽（4）的单晶半导体衬底（2）和（8）的多晶半导体衬底（10）形成其侧壁，其底部的提供（6）。 所述侧壁（6）和底部（8）之间是由绝缘材料制成的过渡区域（12）。 选择性地向所述过渡区域（12）的材料，半导体层被沉积，以便在侧壁（6），一个外延半导体层（24）和在地板（8）生长半导体层（26），仍然存在间隙，该间隙之间。 所沉积的半导体层（24，26）被填充覆盖有薄的，电流的流动仅部分地限定电介质（28）和用导电材料（30）的中间空间。 在随后的热处理中，掺杂剂从所述外延半导体层（26）在导电材料（30）扩散并形成一个掺杂区（44）。 限定在一方面薄电介质（28），在半导体衬底（2）和在另一方面的掺杂物的扩散它可以防止晶体的晶格缺陷的扩散的外延半导体层（26）英寸

公开(公告)号：DE10255866B4

公开(公告)日：2006-11-23

申请号：DE10255866

申请日：2002-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUETZEN JOERN ,  BIRNER ALBERT ,  KUDELKA STEPHAN ,  TEWS HELMUT ,  WEIS ROLF

IPC: H01L21/306 ,  H01L27/108 ,  H01L21/302 ,  H01L21/308 ,  H01L21/461 ,  H01L21/8242 ,  H01L29/04

Abstract: A process for increasing the structural density (thickness, sic) and/or storage capacity of structures introduced into a semiconductor wafer (1) by marking (2) in the rupture direction, where the structures by means of a light exposure device and a mask (3) are formed on the wafer. Before formation of the structures the wafer is turned by 45 deg in its plane and is given a marking in a new direction parallel to a (100) crystal orientation. A process for increasing the structural size (density, sic) of main structures (MS) formed in the bulk of a SS by an etching process, in which main structures on one surface of the SS are exchanged in a surface section of the SS by secondary structures arranged in a surface screen (14) and directed with longitudinal and transverse extension parallel to the x and y axes of the surface screen where before etching the longitudinal and transverse extensions of the main structures are twisted relative to the x and y axes of surface screen so that the section of the SS below the secondary MS main structures is made completely available for formation of further MS by means of a further etching process. Independent claims are included for: (1) a structure in a SS comprising a drain with a limiting upper section at the surface of the SS of plan view surface profile with longitudinal sides parallel to the (100) crystal orientation and with rectangular profile in a lower section below an etch resistant protective layer with longitudinal sides parallel to the (110) crystal orientation; (2) an arrangement of structures in which the thickness of the intermediate walls between adjacent structures in the SS is of the order of 100 nm; (3) a process for reduction of leakage current in a selection transistor and a DRAM-cell with storage capacity, where DRAM = dynamic random access memory, with processing of a semiconductor wafer having a DRAM-cell; (4) a DRAM-cell obtained as above and having storage capacity.

公开(公告)号：DE102004031453A1

公开(公告)日：2006-02-09

申请号：DE102004031453

申请日：2004-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  WEBER ANDREAS ,  SCHLOESSER TILL ,  LUETZEN JOERN

IPC: H01L21/314 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8242

Abstract: The present invention relates to a method for producing a dielectric on a semiconductor body having the following steps that are to be performed successively: provision of a semiconductor body, application of a dielectric layer on at least parts of a first surface of the semiconductor body in such a way as at least partly to form an interface between the dielectric layer and the semiconductor body, and thermal annealing of the semiconductor body and the dielectric layer. The method according to the invention is distinguished by the fact that temporally prior to the annealing, for the purpose of improving the saturation and the electrical properties, fluorine-containing particles are introduced into regions of the semiconductor body and/or of the dielectric layer which adjoin the interface. The present invention furthermore relates to a corresponding semiconductor structure.