公开(公告)号：US20160197037A1

公开(公告)日：2016-07-07

申请号：US15049500

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US09241423B2

公开(公告)日：2016-01-19

申请号：US13860937

申请日：2013-04-11

Applicant: INTEL CORPORATION

Inventor： Chia-Pin Chiu

IPC: H05K7/20 ,  H05K1/00 ,  H01R13/46 ,  H05K3/30 ,  F28F9/00 ,  F28F3/12 ,  H01L23/473 ,  F04B17/00

CPC classification number: H05K7/20254 ,  F04B17/00 ,  F28F3/12 ,  H01L23/473 ,  H01L2924/0002 ,  H05K7/20 ,  H05K7/20236 ,  H01L2924/00

Abstract: A heat dissipation device that includes a base plate having a plurality of substantially circular channels which are substantially concentrically arranged; and a fluid distribution structure adjacent the base plate, wherein the fluid distribution structure has a plurality of inlet conduits extending substantially radially from a central area with each of the plurality of inlet conduits having at least one fluid delivery port extending through the fluid distribution structure to at least one base plate circular channel, and wherein the fluid distribution structure has a plurality of outlet zones defined between adjacent inlet conduits with each of the plurality of outlet zones having at least one fluid removal port extending through the fluid distribution structure to at least one base plate circular channel.

Abstract translation: 一种散热装置，包括：基板，具有基本同心配置的多个基本圆形的通道; 以及邻近所述基板的流体分配结构，其中所述流体分配结构具有多个从中心区域大致径向延伸的入口导管，所述多个入口管道中的每一个具有延伸穿过所述流体分配结构的至少一个流体输送端口， 至少一个基板圆形通道，并且其中所述流体分配结构具有限定在相邻入口管道之间的多个出口区域，所述多个出口区域中的每一个具有延伸穿过所述流体分配结构的至少一个流体移除端口至少一个 基板圆形通道。

公开(公告)号：US09171816B2

公开(公告)日：2015-10-27

申请号：US14663689

申请日：2015-03-20

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract translation: 这里通常讨论的是包括骰子之间的高密度互连和用于制造和使用这些设备的技术的设备。 在一个或多个实施例中，器件可以包括无冲突构建层（BBUL）衬底，其包括至少部分地嵌入在BBUL衬底中的第一管芯，第一管芯包括第一多个高密度互连焊盘。 第二管芯可以至少部分地嵌入在BBUL衬底中，第二管芯包括第二多个高密度互连焊盘。 高密度互连元件可以嵌入在BBUL基板中，高密度互连元件包括电耦合到第一和第二多个高密度互连焊盘的第三多个高密度互连焊盘。

公开(公告)号：US09153552B2

公开(公告)日：2015-10-06

申请号：US14570785

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/00 ,  H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/538 ,  H01L23/36 ,  H01L21/56 ,  H01L23/34

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract translation: 一个实例包括包括具有下模表面的微电子管芯，平行于下模表面的上模表面和管芯侧的管芯封装，该微电子管芯包括有源区和非活性区。 该实施例可选地包括具有较低散热器表面的散热器，平行于下部散热器表面的上部散热器表面和至少一个散热器侧，散热器布置在热电连接的微电子管芯的上表面上 具有裸片的非活性区域并与活性区电绝缘。 该实施例可选地包括封装模具侧和散热器侧和下部散热器表面的封装材料，该封装材料包括基本上平行于模具下表面的下表面和基本上平行于模具上表面的上表面。

公开(公告)号：US12293956B2

公开(公告)日：2025-05-06

申请号：US17356014

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Jin Yang ,  Jimmy Chuang ,  Xicai Jing ,  Yuan-Liang Li ,  Yuyang Xia ,  David Shia ,  Mohanraj Prabhugoud ,  Maria de la Luz Belmont ,  Oscar Farias Moguel ,  Andres Ramirez Macias ,  Javier Avalos Garcia ,  Jessica Gullbrand ,  Shaorong Zhou ,  Chia-Pin Chiu ,  Xiaojin Gu

IPC: H01L23/44

Abstract: An apparatus is described. The apparatus includes a packaged semiconductor device. The packaged semiconductor device having an integrated heat spreader, wherein, a boiling enhancement structure exists on the integrated heat spreader without a block mass residing between the boiling enhancement structure and the integrated heat spreader. The boiling enhancement structure has a structured non-planar surface to promote bubble nucleation in an immersion cooling system.

公开(公告)号：US20240402442A1

公开(公告)日：2024-12-05

申请号：US18326458

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Xiaoqian Li ,  Kaveh Hosseini ,  Tim T. Hoang

IPC: G02B6/42

Abstract: The substrate of an integrated circuit component comprises a cutout that extends fully or partially through the substrate. An edge of a photonic integrated circuit (PIC) in the integrated circuit component is coplanar with a wall of the cutout or extends into the cutout. An optical fiber in an FAU is aligned with a waveguide within the PIC and the FAU is attached to the PIC edge and an attachment block. The attachment block provides an increased attachment surface area for the FAU. A portion of the FAU extends into the substrate cutout. A stress relief mechanism can secure the fiber optic cable attached to the FAU to the substrate to at least partially isolate the FAU-PIC attachment from external mechanical forces applied to the optical fiber cable. The integrated circuit component can be attached to a socket that comprises a socket cutout into which an FAU can extend.

公开(公告)号：US12099245B2

公开(公告)日：2024-09-24

申请号：US17125481

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Asako Toda ,  Chia-Pin Chiu ,  Xiaoqian Li ,  Yiqun Bai

IPC: G02B6/42

CPC classification number: G02B6/4253 ,  G02B6/4243 ,  G02B6/4268 ,  G02B6/4269

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, where the package substrate comprises a recessed edge. In an embodiment, a compute die is on the package substrate, and an optics die on the package substrate and overhanging the recessed edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the optics die. In an embodiment, a lid covers the recess in the package substrate.

公开(公告)号：US11854931B2

公开(公告)日：2023-12-26

申请号：US16721807

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Chia-Pin Chiu ,  Peng Li ,  Shankar Devasenathipathy

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/5386 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2225/06589

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

公开(公告)号：US11824008B2

公开(公告)日：2023-11-21

申请号：US17956761

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

CPC classification number: H01L23/5385 ,  H01L23/13 ,  H01L23/5381 ,  H01L24/14 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L21/6835 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/49175 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0401 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/00011 ,  H01L2224/0401

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20230369289A1

公开(公告)日：2023-11-16

申请号：US17742799

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Jong-Ru Guo ,  Zhen Zhou ,  Jason Mix ,  Chia-Pin Chiu ,  Zuoguo Wu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49838 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06548

Abstract: Embodiments of a microelectronic assembly comprise a package substrate, a first integrated circuit (IC) die, a second IC die between the first IC die and the package substrate, a dielectric material between the first IC die and the package substrate, and a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate. The microelectronic assembly is in a space defined by three mutually orthogonal axes, a first axis, a second axis and a third axis; the package substrate, the first IC die and the second IC die are mutually parallel in first planes defined by the first axis and the third axis; the vias are in one or more second planes defined by the second axis and the third axis; and the vias are inclined at an angle not equal to ninety degrees around the first axis.