公开(公告)号：US20250103430A1

公开(公告)日：2025-03-27

申请号：US18907092

申请日：2024-10-04

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Nikos Kaburlasos ,  Lidong Xu ,  Subramaniam Maiyuran ,  Altug Koker ,  Naveen Matam ,  James Holland ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Durgaprasad Bilagi ,  Xinmin Tian

IPC: G06F11/10 ,  G06F12/0802 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

公开(公告)号：US12243496B2

公开(公告)日：2025-03-04

申请号：US18322665

申请日：2023-05-24

Applicant: Intel Corporation

Inventor： Arthur J. Runyan ,  Richmond Hicks ,  Nausheen Ansari ,  Narayan Biswal ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee ,  Joydeep Ray ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Scott Janus ,  Gary Smith ,  Nilesh V. Shah ,  Keith W. Rowe ,  Robert J. Johnston

IPC: G09G3/34 ,  B60K35/22 ,  B60R1/24 ,  G02B27/01 ,  G06F3/147 ,  G09G3/36 ,  G09G5/00 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  B60K35/21 ,  B60K35/215 ,  B60K35/40 ,  B60K35/60 ,  B60K35/81

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

公开(公告)号：US20250046001A1

公开(公告)日：2025-02-06

申请号：US18800406

申请日：2024-08-12

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Arthur Hunter ,  Kamal Sinha ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T17/20

Abstract: Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

公开(公告)号：US12210477B2

公开(公告)日：2025-01-28

申请号：US17428530

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US12094048B2

公开(公告)日：2024-09-17

申请号：US17497618

申请日：2021-10-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Arthur Hunter ,  Kamal Sinha ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T17/20

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T17/20

Abstract: Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

公开(公告)号：US12013808B2

公开(公告)日：2024-06-18

申请号：US17429873

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ben Ashbaugh ,  Scott Janus ,  Aravindh Anantaraman ,  Abhishek R. Appu ,  Niranjan Cooray ,  Varghese George ,  Arthur Hunter ,  Brent E. Insko ,  Elmoustapha Ould-Ahmed-Vall ,  Selvakumar Panneer ,  Vasanth Ranganathan ,  Joydeep Ray ,  Kamal Sinha ,  Lakshminarayanan Striramassarma ,  Prasoonkumar Surti ,  Saurabh Tangri

IPC: G06F13/38 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

公开(公告)号：US20230386417A1

公开(公告)日：2023-11-30

申请号：US18322665

申请日：2023-05-24

Applicant: Intel Corporation

Inventor： Arthur J. Runyan ,  Richmond Hicks ,  Nausheen Ansari ,  Narayan Biswal ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee ,  Joydeep Ray ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Scott Janus ,  Gary Smith ,  Nilesh V. Shah ,  Keith W. Rowe ,  Robert J. Johnston

IPC: G09G3/34 ,  G09G3/36 ,  B60R1/00 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  G06F3/147 ,  G02B27/01 ,  G09G5/00 ,  B60R1/24

CPC classification number: G09G3/3406 ,  G09G3/3648 ,  B60R1/00 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  G06F3/147 ,  G02B27/01 ,  G09G5/00 ,  B60R1/24 ,  G09G2360/144 ,  G09G2320/0626 ,  G09G2380/10 ,  B60R2300/205 ,  B60R2300/207 ,  B60R2300/302 ,  B60R2300/802 ,  B60K2370/21 ,  B60K2370/31 ,  B60K2370/34 ,  B60K2370/37 ,  B60K2370/52 ,  B60K2370/77 ,  B60K2370/152 ,  B60K2370/154 ,  B60K2370/155 ,  B60K2370/334 ,  G09G2340/0464 ,  G09G2354/00

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

公开(公告)号：US11699404B2

公开(公告)日：2023-07-11

申请号：US17703645

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Arthur J. Runyan ,  Richmond Hicks ,  Nausheen Ansari ,  Narayan Biswal ,  Ya-Ti Peng ,  Abhishek R. Appu ,  Wen-Fu Kao ,  Sang-Hee Lee ,  Joydeep Ray ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Scott Janus ,  Gary Smith ,  Nilesh V. Shah ,  Keith W. Rowe ,  Robert J. Johnston

IPC: B60R1/00 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  G06F3/147 ,  G02B27/01 ,  G09G5/00 ,  B60R1/24 ,  G09G3/34 ,  G09G3/36

CPC classification number: G09G3/3406 ,  B60R1/00 ,  B60R1/24 ,  G02B27/01 ,  G06F3/147 ,  G09G3/3648 ,  G09G5/00 ,  G09G5/10 ,  G09G5/14 ,  G09G5/38 ,  B60K2370/152 ,  B60K2370/154 ,  B60K2370/155 ,  B60K2370/21 ,  B60K2370/31 ,  B60K2370/334 ,  B60K2370/34 ,  B60K2370/37 ,  B60K2370/52 ,  B60K2370/77 ,  B60R2300/205 ,  B60R2300/207 ,  B60R2300/302 ,  B60R2300/802 ,  G09G2320/0626 ,  G09G2340/0464 ,  G09G2354/00 ,  G09G2360/144 ,  G09G2380/10

Abstract: Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

公开(公告)号：US11676322B2

公开(公告)日：2023-06-13

申请号：US17500631

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Darrel Palke ,  Sherine Abdelhak ,  Jill Boyce ,  Varghese George ,  Scott Janus ,  Adam Lake ,  Zhijun Lei ,  Zhengmin Li ,  Mike Macpherson ,  Carl Marshall ,  Selvakumar Panneer ,  Prasoonkumar Surti ,  Karthik Veeramani ,  Deepak Vembar ,  Vallabhajosyula Srinivasa Somayazulu

IPC: G06T17/20 ,  G06N3/08 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20 ,  G06T15/00

CPC classification number: G06T15/005 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T17/20

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US11627307B2

公开(公告)日：2023-04-11

申请号：US17252843

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Changliang Wang ,  Ximin Zhang ,  Jill Boyce ,  Sang-Hee Lee ,  Scott Janus ,  Yunbiao Lin

IPC: H04N7/12 ,  H04N19/102 ,  H04N19/146

Abstract: Embodiments are generally directed to transport controlled video coding. An embodiment of an apparatus includes one or more processors to process data; a memory to store data, including data for video streaming; and a video processing mechanism including an encoder and a transport mechanism, wherein the video processing mechanism is to generate a prediction of channel throughput for a network channel, encode one or more bitstreams based on the prediction, including encoding a plurality of bitstreams including a first bitstream and a second bitstream if the prediction indicates an increase or decrease in channel throughput and encoding a single bitstream if the prediction indicates a stable channel throughput; and select a bitstream of the one or more bitstreams for a current frame.