公开(公告)号：US20080042518A1

公开(公告)日：2008-02-21

申请号：US11465319

申请日：2006-08-17

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: H01L41/113

CPC classification number: H01H59/0009 ,  H01H1/50 ,  H01H11/0062 ,  H01H47/002 ,  H01H2057/006 ,  H01H2201/02

Abstract: A micro electromechanical switch has a movable portion positioned to form an electrical connection between a first electrical contact and a second electrical contact. A piezoelectric electrode is formed on the movable portion. The piezoelectric electrode causes the movable portion to move in response to a driver voltage. A piezo element is formed on the movable portion of the switch. The piezo element is for detecting movement of the movable portion between an open position and a closed position. The piezo element is also used to detect switch bouncing when the switch transitions from the open position to the closed position. In one embodiment, the piezo element is a piezoelectric element and in another embodiment the piezo element is a piezo-resistive element.

Abstract translation: 微机电开关具有可移动部分，其被定位成在第一电接触件和第二电接触件之间形成电连接。 压电电极形成在可动部分上。 压电电极使可动部分响应于驱动器电压而移动。 压电元件形成在开关的可移动部分上。 压电元件用于检测可动部分在打开位置和关闭位置之间的移动。 当开关从打开位置转换到关闭位置时，压电元件还用于检测开关跳动。 在一个实施例中，压电元件是压电元件，在另一个实施例中，压电元件是压电元件。

公开(公告)号：US20070281438A1

公开(公告)日：2007-12-06

申请号：US11444091

申请日：2006-05-31

Applicant: Lianjun Liu ,  Philip H. Bowles ,  Li Li

Inventor： Lianjun Liu ,  Philip H. Bowles ,  Li Li

IPC: H01L21/30

CPC classification number: H01L23/5225 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A patterned ground shield (PGS) (130) in a vertically-integrated structure includes a patterned conductor (e.g., a metallic layer) provided between a first substrate (110) having a first semiconductor device (1120 formed therein and a second substrate (120) having a second device (122) formed therein. A bonding layer (140) is used to bond the vertically-integrated die and/or wafers. The PGS may be formed on a surface (e.g., the backside) of the second (topmost) substrate, or may be formed over the first semiconductor device—for example, on a dielectric layer formed over the first semiconductor device. The PGS may consist of parallel stripes in various patterns, or may be spiral-shaped, lattice-shaped, or the like.

Abstract translation: 在垂直一体化结构中的图案化接地屏蔽（PGS）（130）包括设置在具有第一半导体器件的第一衬底（1120）和第二衬底（120）之间的图案化导体（例如，金属层） ），其中形成有第二器件（122），接合层（140）用于将垂直集成的裸片和/或晶片接合，PGS可以形成在第二（顶部）的表面（例如，背面）上 或者可以形成在第一半导体器件上，例如在形成于第一半导体器件上的电介质层上，PGS可以由各种图案的平行条纹组成，或者可以是螺旋状，格子状或 类似。

公开(公告)号：US06809036B2

公开(公告)日：2004-10-26

申请号：US10259808

申请日：2002-09-30

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: H01L21302

CPC classification number: H01J37/321 ,  G03F7/265 ,  G03F7/36

Abstract: A dry silylation process involving plasma etching of a substrate (100) having an upper surface (100S) coated with a first layer (L1) of silylatable material with one or more silylated regions (S1, S2) formed therein. The plasma (66) is oxygen-based plasma having a first region (66L) with a low plasma density and high radical density, and a second region (66U) having a high plasma density and a low radical density. The process includes the steps of exposing the one or more silylated regions to the first plasma region to form respective one or more oxidized regions (OR1, OR2) from the one or more silylated regions. The next step is then exposing the substrate to the second plasma region to selectively etch the silylatable material that is directly exposed to the plasma. The process of the present invention can be used, for example, to form photoresist patterns (P) having straight (vertical) sidewalls (SW) in the fabrication of a semiconductor device.

Abstract translation: 一种干法硅烷化方法，涉及对具有上述表面（100S）进行等离子体蚀刻的基板（100），该上表面（100S）涂覆有在其中形成有一个或多个甲硅烷基化区域（S1，S2）的可甲硅烷化材料的第一层（L1）。 等离子体（66）是具有低等离子体密度和高自由基密度的第一区域（66L）的氧基等离子体和具有高等离子体密度和低自由基密度的第二区域（66U）。 该方法包括将一个或多个甲硅烷基化区域暴露于第一等离子体区域以从一个或多个甲硅烷基化区域形成相应的一个或多个氧化区域（OR1，OR2）的步骤。 接下来的步骤是将衬底暴露于第二等离子体区域以选择性地蚀刻直接暴露于等离子体的可甲硅烷化材料。 本发明的方法可以用于在制造半导体器件时形成具有直（垂直）侧壁（SW）的光刻胶图案（P）。

公开(公告)号：US06706548B2

公开(公告)日：2004-03-16

申请号：US10041337

申请日：2002-01-08

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: H01L24763

CPC classification number: B81B7/0006

Abstract: A method of making a micromechanical device including forming recesses (28) using two sacrificial layers (22 and 27). A first sacrificial layer (22) is formed over an input signal line (16) and an output signal line (17). A portion of the first sacrificial layer (22) is removed to form openings (26) over the input signal line (16) and the output signal line (17). A second sacrificial layer (27) is formed over the first sacrificial layer (22) and openings (26) to form recesses (28) over the openings (26). A conductive layer (32) is formed over the second sacrificial layer (27) and the recesses (28). The conductive layer (32) serves as a shorting bar of a cantilever beam structure that couples input signal line (16) to output signal line (17) during operation.

Abstract translation: 一种制造微机械装置的方法，包括使用两个牺牲层（22和27）形成凹部（28）。 第一牺牲层（22）形成在输入信号线（16）和输出信号线（17）上。 去除第一牺牲层（22）的一部分以在输入信号线（16）和输出信号线（17）上形成开口（26）。 第二牺牲层（27）形成在第一牺牲层（22）上方，并且开口（26）在开口（26）之上形成凹陷（28）。 在第二牺牲层（27）和凹部（28）之上形成导电层（32）。 导电层（32）用作在操作期间将输入信号线（16）耦合到输出信号线（17）的悬臂梁结构的短路棒。

公开(公告)号：US06225140B1

公开(公告)日：2001-05-01

申请号：US09170732

申请日：1998-10-13

Applicant: Lianjun Liu ,  Zhe Wang

Inventor： Lianjun Liu ,  Zhe Wang

IPC: H01L21302

CPC classification number: G01L19/0618 ,  G01L9/0042 ,  G01L9/0054

Abstract: A pressure sensor and method of forming the pressure sensor are described. The pressure sensor is formed by etching a number of trenches in a silicon substrate. Dielectric spacers are formed on the sidewalls of the trenches. The bottoms of the trenches are then etched using isotropic etching to undercut the sidewalls of the trenches and form a number of silicon bridges with a limited gap between the underside of the bridges and the bulk silicon substrate. A filler dielectric is then deposited to fill the gaps between the sidewalls of the trenches thereby forming a flexible membrane. Piezoresistors are formed in the silicon bridges or, alternatively, on the flexible membrane. Pressure changes deflect the flexible membrane causing resistance changes in the piezoresistors which can be monitored and related to pressure. The limited gap between the underside of the bridges and the bulk silicon substrate provides overpressure protection for the sensor.

Abstract translation: 描述了形成压力传感器的压力传感器和方法。 压力传感器通过蚀刻硅衬底中的多个沟槽而形成。 电介质隔板形成在沟槽的侧壁上。 然后使用各向同性蚀刻来蚀刻沟槽的底部，以切割沟槽的侧壁并形成多个在桥的底部和体硅衬底之间具有有限间隙的硅桥。 然后沉积填料电介质以填充沟槽的侧壁之间的间隙，从而形成柔性膜。 在硅桥中或者在柔性膜上形成压阻器。 压力变化使柔性膜偏转导致压敏电阻器的电阻变化，可以监测并与压力有关。 桥的底面和体硅衬底之间的有限的间隙为传感器提供过压保护。

公开(公告)号：US5705428A

公开(公告)日：1998-01-06

申请号：US511063

申请日：1995-08-03

Applicant: Lianjun Liu ,  Chiu-Kwan Man

Inventor： Lianjun Liu ,  Chiu-Kwan Man

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/44

CPC classification number: H01L21/31138 ,  H01L21/32135 ,  H01L21/32136

Abstract: A process for forming metal composites, using a titanium underlay as part of the composite, with reduced risk of titanium adhesion loss or lifting, has been developed. Several solutions, resulting in protective layers being formed on the exposed titanium sidewall, have been shown. One solution features the addition of nitrogen, as part of reactive ion etching chemistry, during the patterning of the underlying titanium layer. The resulting titanium nitride formation, on the exposed titanium sidewall, protects against subsequent processing steps that may degrade the adhesion of titanium to an underlying material. A second solution describes the formation of a titanium oxide film on the exposed titanium sidewall. This formation occurs during a photoresist plasma strip, using an oxygen-stream ambient. The titanium oxide film again results in protection of the titanium interface, during subsequent processing steps.

Abstract translation: 已经开发了使用钛底层作为复合材料的一部分形成金属复合材料的方法，其具有降低的钛粘合损失或提升的风险。 已经示出了在暴露的钛侧壁上形成保护层的几种解决方案。 一种解决方案是在下层钛层的图案化期间添加氮作为反应离子蚀刻化学的一部分。 在暴露的钛侧壁上产生的氮化钛形成可防止可能降低钛与下层材料的粘附性的后续加工步骤。 第二个解决方案描述了在暴露的钛侧壁上形成氧化钛膜。 这种形成发生在光致抗蚀剂等离子体条中，使用氧流环境。 在随后的加工步骤中，氧化钛膜再次导致钛界面的保护。

公开(公告)号：US09958471B2

公开(公告)日：2018-05-01

申请号：US14004838

申请日：2012-02-23

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: G01P15/125 ,  B81C1/00 ,  G01P15/18 ,  G01C19/5769 ,  G01P15/08

CPC classification number: G01P15/125 ,  B81C1/00341 ,  G01C19/5769 ,  G01P15/0802 ,  G01P15/18 ,  G01P2015/0814

Abstract: A MEMS inertial sensor, may include a movable sensitive element; and second substrate and a third substrate. The movable sensitive element may be formed by using a first substrate which may be formed of a monocrystalline semiconductor material. The first substrate may include a first surface and a second surface which are opposite to each other. One or more conductive layers may be formed on the first surface of the first substrate The second substrate may be coupled to a surface of the one or more conductive layer on the first substrate. The third substrate may be coupled to the second surface of the first substrate. The third substrate and the second substrate are respectively arranged on two opposite sides of the movable sensitive element.

公开(公告)号：US09926187B2

公开(公告)日：2018-03-27

申请号：US14537498

申请日：2014-11-10

Applicant: Chad S Dawson ,  Dubravka Bilic ,  Lianjun Liu ,  Andrew C McNeil

Inventor： Chad S Dawson ,  Dubravka Bilic ,  Lianjun Liu ,  Andrew C McNeil

IPC: G01L9/12 ,  B81B3/00 ,  G01L9/00

CPC classification number: B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  G01L9/0072

Abstract: Methods for fabricating crack resistant Microelectromechanical (MEMS) devices are provided, as are MEMS devices produced pursuant to such methods. In one embodiment, the method includes forming a sacrificial body over a substrate, producing a multi-layer membrane structure on the substrate, and removing at least a portion of the sacrificial body to form an inner cavity within the multi-layer membrane structure. The multi-layer membrane structure is produced by first forming a base membrane layer over and around the sacrificial body such that the base membrane layer has a non-planar upper surface. A predetermined thickness of the base membrane layer is then removed to impart the base membrane layer with a planar upper surface. A cap membrane layer is formed over the planar upper surface of the base membrane layer. The cap membrane layer is composed of a material having a substantially parallel grain orientation.

公开(公告)号：US09720051B2

公开(公告)日：2017-08-01

申请号：US14290040

申请日：2014-05-29

Applicant: Paige M. Holm ,  Lianjun Liu

Inventor： Paige M. Holm ,  Lianjun Liu

IPC: G01R33/09 ,  G01R33/00 ,  G01R35/00

CPC classification number: G01R33/0023 ,  G01R33/09 ,  G01R35/005

Abstract: A magnetic field sensor includes in-plane sense elements located in a plane of the magnetic field sensor and configured to detect a magnetic field oriented perpendicular to the plane. A current carrying structure is positioned proximate the magnetic field sensor and includes at least one coil surrounding the in-plane sense elements. An electric current is applied to the coil to create a self-test magnetic field to be sensed by the sense elements. The coil may be vertically displaced from the plane in which the sense elements are located and laterally displaced from an area occupied by the sense elements to produce both Z-axis magnetic field components and lateral magnetic field components of the self-test magnetic field. The sense elements are arranged within the coil and interconnected to cancel the lateral magnetic field components, while retaining the Z-axis magnetic field components to be used for self-test of the magnetic field sensor.

公开(公告)号：US09633952B2

公开(公告)日：2017-04-25

申请号：US14111093

申请日：2012-02-23

Applicant: Lianjun Liu

Inventor： Lianjun Liu

IPC: H01L21/764 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L21/84 ,  H01L21/762 ,  H01L21/30 ,  H01L23/544 ,  H01L25/00 ,  B81C1/00

CPC classification number: H01L23/562 ,  B81C1/00182 ,  B81C1/00365 ,  B81C2201/019 ,  H01L21/30 ,  H01L21/76283 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate.