公开(公告)号：WO1997044160A1

公开(公告)日：1997-11-27

申请号：PCT/US1997008786

申请日：1997-05-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ROBINSON, Karl, M. ,  WALKER, Michael, A.

IPC: B24B37/04

CPC classification number: B24B37/015 ,  H01L21/31053

Abstract: The present invention is a method for chemical-mechanical planarization of semiconductor wafers that is highly useful for planarizing stop-on-feature design wafers. Initially, the wafer is positioned against a liquid solution over a planarizing surface of a polishing pad. At least one of the wafer or the pad is moved with respect to the other at a relatively low velocity to maintain a substantially continuous film of liquid solution between the wafer and the pad. The temperature of a pad platen is also controlled to maintain a relatively low temperature of the liquid solution at which the solution is highly selective to a layer of material on the wafer.

Abstract translation: 本发明是半导体晶片的化学机械平面化方法，其对于平坦化停止特征设计晶片是非常有用的。 最初，将晶片相对于抛光垫的平坦化表面上的液体溶液定位。 晶片或焊盘中的至少一个以相对低的速度相对于另一个移动，以在晶片和焊盘之间维持基本上连续的液体溶液膜。 焊盘压板的温度也被控制以保持溶液对晶片上的材料层具有高度选择性的液体溶液的较低温度。

公开(公告)号：WO1997040444A1

公开(公告)日：1997-10-30

申请号：PCT/US1997006348

申请日：1997-04-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MERRITT, Todd, A.

IPC: G06F11/20

CPC classification number: G11C29/70 ,  G11C7/1006 ,  G11C29/81

Abstract: The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more "planes". Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory. As a result, the present invention saves on the number of lines required to intercouple the compare circuits to the redundant rows/columns.

Abstract translation: 本发明通过基于主存储器阵列分成两个或更多个“平面”，通过与冗余存储器单元组共享比较电路来减少冗余存储器单元的行和列所需的存储体上的面积。 耦合在至少两组熔丝之间的通过门或多路复用器，并且一个比较电路选择性地将适当的熔丝组耦合到比较电路。 优选地，地址中的位（例如，具有地址位A0-RA9的行地址字中的地址位RA9）被控制多路复用器在两组保险丝之间进行选择。 此外，这些平面跨越存储器阵列中的存储器块，其中每个块由共享读出放大器划分。 结果是，当八行连接到16行或列时，只有8行或任何列在任何一个时刻都将被激活，因为隔离栅将仅使存储器的两个平面内的16行或列中的八个。 结果，本发明节省了将比较电路与冗余行/列相互耦合所需的行数。

公开(公告)号：WO1997028560A1

公开(公告)日：1997-08-07

申请号：PCT/US1997001729

申请日：1997-01-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  LEE, Ruojia ,  THAKUR, Randhir, P., S.

IPC: H01L21/28

CPC classification number: H01L29/66651 ,  H01L21/28167 ,  H01L21/28211

Abstract: This invention improves the quality of gate oxide dielectric layers using a two-pronged approach, thus permitting the use of much thinner silicon dioxide gate dielectric layers required for lower-voltage, ultra-dense integrated circuits. In order to eliminate defects caused by imperfections in bulk silicon, an in-situ grown epitaxial layer is formed on active areas following a strip of the pad oxide layer used beneath the silicon nitride islands used for masking during the field oxidation process. By growing an epitaxial silicon layer prior to gate dielectric layer formation, defects in the bulk silicon substrate are covered over and, hence, isolated from the oxide growth step. In order to maintain the integrity of the selective epitaxial growth step, the wafers are maintained in a controlled, oxygen-free environment until the epitaxial growth step is accomplished. In order to eliminate defects caused by a native oxide layer, the wafers are maintained in a controlled, oxygen-free environment until being subjected to elevated temperature in a controlled, oxidizing environment. In one embodiment, the oxidizing environment comprises diatomic oxygen, while in another embodiment, the oxidizing environment comprises diatomic oxygen and ozone.

Abstract translation: 本发明使用双管齐下的方法提高了栅极氧化物电介质层的质量，从而允许使用更低的，超低密度集成电路所需的更薄的二氧化硅栅介质层。 为了消除体硅缺陷引起的缺陷，在场氧化工艺中用于掩蔽的氮化硅岛下方的氧化硅层之后的有源区上形成原位生长的外延层。 通过在栅介质层形成之前生长外延硅层，将体硅衬底中的缺陷覆盖并因此从氧化物生长步骤中分离。 为了保持选择性外延生长步骤的完整性，将晶片保持在受控的无氧环境中，直到外延生长步骤完成。 为了消除由自然氧化物层引起的缺陷，将晶片保持在受控制的无氧环境中，直到在受控的氧化环境中经历升高的温度。 在一个实施方案中，氧化环境包括双原子氧，而在另一个实施方案中，氧化环境包括双原子氧和臭氧。

公开(公告)号：WO1997026114A1

公开(公告)日：1997-07-24

申请号：PCT/US1997000861

申请日：1997-01-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ROBINSON, Karl, M.

IPC: B24D03/28

CPC classification number: B24B37/245 ,  B24B37/24 ,  B24D3/28 ,  Y10S451/921

Abstract: The present invention is a polishing pad for use in chemical-mechanical planarization of semiconductor wafers, and a method for making the polishing pad. The polishing pad has a body, molecular bonding links, and abrasive particles dispersed substantially uniformly throughout the body. The body is made from a polymeric matrix material and the molecular bonding links are covalently bonded to the matrix material. Substantially all of the abrasive particles are covalently bonded to at least one molecular bonding link. The molecular bonding links securely affix the abrasive particles to the matrix material to enhance the uniformity of the distribution of the abrasive particles throughout the pad and to substantially prevent the abrasive particles from breaking away from the pad.

Abstract translation: 本发明是用于半导体晶片的化学机械平面化的抛光垫及其制造方法。 抛光垫具有主体，分子连接链和基本均匀地分布在整个体内的磨料颗粒。 主体由聚合物基质材料制成，分子键合链与基质材料共价键合。 基本上所有的磨料颗粒共价键合到至少一个分子键合连接。 分子键合连接牢固地将磨料颗粒固定在基质材料上，以增强研磨剂颗粒在整个垫中的分布的均匀性，并且基本上防止磨料颗粒从垫上脱落。

公开(公告)号：WO1997015836A1

公开(公告)日：1997-05-01

申请号：PCT/US1995013708

申请日：1995-10-24

Applicant: MICRON TECHNOLOGY, INC. ,  HEMBREE, David, R. ,  FARNWORTH, Warren, M. ,  WOOD, Alan, G.

Inventor： MICRON TECHNOLOGY, INC.

IPC: G01R31/28

CPC classification number: G01R31/2886 ,  G01R1/0483 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: Optical alignment techniques, such as those used in "flip chip" bonding, are used to establish ohmic contact with die (24) by means of raised portions on contact members (20). This permits accurate alignment with a temporary die fixture (10) in order to test the die (24). The tested die (24) can then be qualified under a known good die program as having an acceptable degree of reliability. This permits the die (24) to be characterized prior to assembly, so that the die (24) may then be transferred in an unpackaged form. This ohmic contact is preferably established by applying a compression force to the die (24) using an interconnect insert (14) resulting in a limited penetration of the contact member (20) into the bondpads (22). The arrangement may be used for establishing electrical contact with a burn-in oven.

Abstract translation: 使用诸如“倒装芯片”接合中使用的那些的光学对准技术通过接触构件（20）上的凸起部分与模具（24）建立欧姆接触。 这允许与临时模具夹具（10）精确对准，以便测试模具（24）。 然后，被测试的模具（24）可以在已知的良好的模具程序下被认证为具有可接受的可靠度。 这允许在组装之前对模具（24）进行表征，使得模具（24）然后可以以未包装的形式传送。 该欧姆接触优选通过使用互连插件（14）向模具（24）施加压缩力而导致接触构件（20）有限地穿透到粘结垫（22）中来建立。 该装置可用于与老化烘箱建立电接触。

公开(公告)号：WO1997008702A1

公开(公告)日：1997-03-06

申请号：PCT/US1996014001

申请日：1996-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  CLOUD, Eugene, H. ,  WILLIAMS, Brett, L. ,  MANNING, Troy, A.

IPC: G11C07/00

CPC classification number: G11C7/1063 ,  G11C7/1051 ,  G11C7/22 ,  G11C11/4076

Abstract: A memory circuit is described which includes memory cells for storing data. The memory circuit can be read from or written to by an external system such as a microprocessor or core logic chip set. The microprocessor provides memory cell address data to the memory circuit and can request that data be output on communication lines for reading therefrom. The memory circuit reduces the time needed to read data stored in the memory by providing a valid output data signal. The valid output data signal indicates that data coupled to the communication lines has stabilized and is therefore valid. Different valid output data signals and trigger circuits for producing the signals are described.

Abstract translation: 描述了包括用于存储数据的存储单元的存储器电路。 存储器电路可以由诸如微处理器或核心逻辑芯片组的外部系统读取或写入。 微处理器向存储器电路提供存储单元地址数据，并且可以请求在通信线路上输出数据以从中读出数据。 存储器电路通过提供有效的输出数据信号来减少读取存储在存储器中的数据所需的时间。 有效输出数据信号表示耦合到通信线路的数据已经稳定，因此是有效的。 描述了用于产生信号的不同的有效输出数据信号和触发电路。

公开(公告)号：WO1996042148A3

公开(公告)日：1996-12-27

申请号：PCT/US1995016220

申请日：1995-12-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  THOMANN, Mark, R. ,  VO, Huy, Thanh ,  HUSH, Glen, E.

IPC: H04Q11/04

公开(公告)号：WO1996041247A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009941

申请日：1996-06-06

Applicant: MICRON TECHNOLOGY, INC. ,  CASPER, Stephen, L.

Inventor： MICRON TECHNOLOGY, INC.

IPC: G05F01/40

CPC classification number: G05F1/465 ,  G05F3/205 ,  G11C5/147

Abstract: A circuit regulates a voltage by controlling a voltage generator. A voltage divider is coupled between the regulated voltage (Vint) and a supply voltage (Vdd), and generates a sense voltage. A clamp circuit (22) is coupled to the divider (24), and reduces the sensitivity between the supply voltage (Vdd) and the regulated voltage (Vint) by substantially prohibiting the voltage across itself from exceeding a predetermined value. A detector circuit (38) is coupled between the divider (24) and the voltage generator, and provides a control signal that deactivates the generator when the sense voltage reaches a first predetermined threshold, and activates the generator when the sense voltage reaches a second predetermined threshold.

Abstract translation: 电路通过控制电压发生器来调节电压。 分压器耦合在调节电压（Vint）和电源电压（Vdd）之间，并产生感测电压。 钳位电路（22）耦合到除法器（24），并通过基本上禁止其自身超过预定值的电压来降低电源电压（Vdd）和调节电压（Vint）之间的灵敏度。 检测器电路（38）耦合在分压器（24）和电压发生器之间，并提供控制信号，当感测电压达到第一预定阈值时，使发生器停用，并且当感测电压达到第二预定阈值时激活发生器 阈。

公开(公告)号：WO1996039004A2

公开(公告)日：1996-12-05

申请号：PCT/US1995015802

申请日：1995-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  THOMANN, Mark, R. ,  VO, Huy, Thanh ,  HUGH, Glen, E.

IPC: H04Q11/04

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/405 ,  H04L2012/5627 ,  H04L2012/5652 ,  H04L2012/5681

Abstract: An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described for transferring ATM data between the SAMs and the DRAM. The transfer circuits and methods include helper flip/flops to latch ATM data for editing prior to storage in the DRAM. Editing of ATM data transferred from the DRAM is also described. Dynamic parity generation and checking is described to detect errors induced during switching.

Abstract translation: 描述包括多端口存储器的ATM交换机。 具有动态随机存取存储器（DRAM）和多个输入和输出串行存取存储器（SAM）的多端口存储器。 描述了用于在SAM和DRAM之间传送ATM数据的高效，灵活的传送电路和方法。 转移电路和方法包括辅助触发器，以在存储在DRAM中之前锁存ATM数据进行编辑。 还描述了从DRAM传送的ATM数据的编辑。 描述动态奇偶校验生成和检查以检测切换期间引起的错误。

公开(公告)号：WO1996038846A1

公开(公告)日：1996-12-05

申请号：PCT/US1996006898

申请日：1996-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MCLAURY, Loren, L. ,  MORGAN, Donald, M.

IPC: G11C07/00

CPC classification number: G11C7/1021 ,  G11C7/1075 ,  G11C8/04 ,  G11C8/12

Abstract: A memory device includes an array of randomly addressable registers. Blocks of the addressable registers are addressable by an address for block writing during a block write cycle. The blocks are of the size n, wherein n is the number of bits per plane of memory being written during the block write cycle. The device further includes a sequential counter for incrementing the address by n during burst mode when a block write is performed during a block write cycle to address a next addressable register of the array of randomly addressable registers.

Abstract translation: 存储器件包括可随机寻址寄存器的阵列。 可寻址寄存器的块可通过块写入周期期间的块写入的地址寻址。 块的大小为n，其中n是在块写入周期期间被写入的每个存储器平面的位数。 该装置还包括一个顺序计数器，用于当在块写入周期期间执行块写入以寻址随机寻址寄存器阵列的下一可寻址寄存器时，在突发模式期间将地址递增n。