公开(公告)号：AT141734T

公开(公告)日：1996-09-15

申请号：AT90901399

申请日：1989-12-21

Applicant: MOTOROLA INC

Inventor： WILSON GREGORY P ,  POTRATZ BRYAN A ,  WALCZAK THOMAS J ,  MULLINS JEFFREY L

IPC: H04B7/26 ,  B21C23/08 ,  B21J5/10 ,  B21J9/04 ,  H03K5/156 ,  H04B20060101 ,  H04B3/60 ,  H04B7/00 ,  H04L5/14 ,  H04L12/40 ,  H04Q7/20 ,  H04Q7/22

Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when another of the bus lines is held in a logic high state.

公开(公告)号：CA2072582C

公开(公告)日：1996-04-09

申请号：CA2072582

申请日：1991-12-18

Applicant: MOTOROLA INC

Inventor： WALCZAK THOMAS J ,  CAHILL STEPHEN V

IPC: H03G3/20 ,  H04B1/04 ,  H04B1/40 ,  H04B1/56 ,  H04B7/005 ,  H04J3/02 ,  H04B7/26

Abstract: A TDMA cellular telephone (600) includes, in its transmit signal path, microphone (608), vocoder (612), data format circuitry (601), quadrature modulator (602), 90 MHz local oscillator (606), transmitter with mixer (604), transmitter filter (618), and antenna (620). In its receive signal path, the TDMA cellular telephone (600) includes receiver filter (622) coupled to antenna (620), quadrature demodulator (624), and data deformat circuitry (625). The channel frequency of TDMA cellular telephone (600) is loaded into synthesizer (616) by microcomputer (614) and applied to transmitter (604) and demodulator (624). TDMA cellular telephone (600) is controlled by microcomputer (614) which includes a memory with a control and signaling computer program stored therein. Transmitter (604) includes novel power control circuitry (100) comprised of variable gain stage (104), mixer (106), bandpass filter (109), and directional coupler (112) in a forward path, and detector (116), A/D converter (118), digital controller (120), and D/A converter (126) in a feedback path.

公开(公告)号：GB2260671B

公开(公告)日：1995-05-24

申请号：GB9225110

申请日：1992-03-09

Applicant: MOTOROLA INC

Inventor： LEMERSAL JR DONALD B ,  WALCZAK THOMAS J ,  GREENE ROBERT I

IPC: H04L27/20

Abstract: A modulator circuit for generating a modulated, DQPSK signal. The modulator circuit includes an encoder for receiving a binary bit stream comprised of bit pairs defining differential phase changes. An encoder receives a bit stream of which bit pairs thereof define differential phase changes. The encoder encodes the bit pairs into codewords which are stored and then supplied to an I-accumulator, a Q-accumulator, and a memory element. The memory element contains pre-multiplied values which are supplied to the I- and the Q-accumulators which add terms of the pre-multiplied values to form I-portions and Q-portions of a DQPSK-modulated signal. The I- and Q-portions may then be supplied to a quadrature modulator.

公开(公告)号：GB2257331B

公开(公告)日：1995-04-26

申请号：GB9217653

申请日：1992-08-19

Applicant: MOTOROLA INC

Inventor： WALCZAK THOMAS J ,  CAHILL STEPHEN V

IPC: H03G3/20 ,  H04B1/04 ,  H04B1/40 ,  H04B1/56 ,  H04B7/005 ,  H04Q7/32 ,  H04B1/38

Abstract: A TDMA cellular telephone (600) includes in its transmit signal path, microphone (608), vocoder (612), data format circuitry (601), quadrature modulator (602), 90 MHz local oscillator (606), transmitter with mixer (604), transmitter filter (618), and antenna (620). In its receive signal path, the TDMA cellular telephone (600) includes receiver filter (622) coupled to antenna (620), quadrature demodulator (624), and data deformat circuitry (625). The channel frequency of TDMA cellular telephone (600) is loaded into synthesizer (616) by microcomputer (614) and applied to transmitter (604) and demodulator (624). TDMA cellular telephone (600) is controlled by microcomputer (614) which includes a memory with a control and signaling computer program stored therein. Transmitter (604) includes novel power control circuitry (100) comprised of variable gain stage (104), mixer (106), bandpass filter (109), and directional coupler (112) in a forward path, and detector (116), A/D converter (118 ), digital controller (120), and D/A converter (126) in a feedback path.

公开(公告)号：DE4191735C2

公开(公告)日：1994-11-10

申请号：DE4191735

申请日：1991-08-02

Applicant: MOTOROLA INC

Inventor： WILSON GREGORY P ,  POTRATZ BRYAN A ,  WALCZAK THOMAS J ,  MULLINS JEFFERY L ,  PRILL MARK E

IPC: H04L69/14 ,  H04L5/02 ,  H04L5/16 ,  H04L25/49 ,  H04L5/22 ,  H04L29/02

Abstract: A multiplexed synchronous/asynchronous data bus (109) is disclosed in which three bus lines (T, R, C) are used to convey bidirectional synchronous data between at least two data devices (605, 607, 609, 611) at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.

公开(公告)号：MX170766B

公开(公告)日：1993-09-13

申请号：MX2570591

申请日：1991-05-08

Applicant: MOTOROLA INC

Inventor： CAHILL STEPHEN V ,  GILLIG STEVEN F ,  WALCZAK THOMAS J

IPC: H04B14/00 ,  H04L27/20 ,  H04L25/00 ,  H04L27/00

Abstract: A pi /4-shift DQPSK modulator modulates a digitized voice signal and other information. An FM modulator modulates the analog voice signal and other information. The FM modulator is coupled to the quadrature mixers (109 and 110) of the pi /4-shift DQPSK modulator. When an FM modulated signal is required, the mixers (109 and 110) are biased (114) to allow carrier feedthrough by applying a fixed, non-zero DC signal to one or both mixers (109 and 110). The carrier is then FM modulated using conventional methods such as voltage-modulation of a phase locked loop (PPL) (113). When pi /4-shift DQPSK is to be generated, the conventional baseband I and Q vector-length signals (101 and 102) are applied to the mixers (109 and 110), and the carrier is left unmodulated by switching (115) out the input signal to the PLL (113). The PPL (113) will then generate only the carrier frequency to be mixed with the I and Q vector-length signals (101 and 102).

公开(公告)号：GB2260671A

公开(公告)日：1993-04-21

申请号：GB9225110

申请日：1992-03-09

Applicant: MOTOROLA INC

Inventor： LEMERSAL JR DONALD B ,  WALCZAK THOMAS J ,  GREENE ROBERT I

IPC: H04L27/20

Abstract: A modulator circuit (150) for generating a modulated, DQPSK signal. The modulator circuit includes an encoder (162) for receiving a binary bit stream comprised of bit pairs defining differential phase changes. An encoder receives a bit stream of which bit pairs thereof define differential phase changes. The encoder encodes the bit pairs into codewords which are stored and then supplied to an I-accumulator (230), a Q-accumulator (236), and a memory element (242). The memory element contains premultiplied values which are supplied to the I- and the Q-accumulators which add terms of the pre-multiplied values to form I-portions and Q-portions of a DQPSK-modulated signal. The I- and Q-portions may then be supplied to a quadrature modulator.

公开(公告)号：AU629759B2

公开(公告)日：1992-10-08

申请号：AU8326991

申请日：1991-08-02

Applicant: MOTOROLA INC

Inventor： WILSON GREGORY P ,  POTRATZ BRYAN A ,  WALCZAK THOMAS J ,  MULLINS JEFFERY L ,  PRILL MARK E

IPC: H04L69/14 ,  H04L5/02 ,  H04L5/16 ,  H04L25/49 ,  H04L5/20

Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.

公开(公告)号：MX9201497A

公开(公告)日：1992-10-01

申请号：MX9201497

申请日：1992-04-01

Applicant: MOTOROLA INC

Inventor： LEMERSAL DONALD B JR ,  WALCZAK THOMAS J ,  GREENE ROBERT I

IPC: H04L27/20 ,  H04L27/04

Abstract: A modulator circuit for generating a modulated, DQPSK signal. The modulator circuit includes an encoder for receiving a binary bit stream comprised of bit pairs defining differential phase changes. An encoder receives a bit stream of which bit pairs thereof define differential phase changes. The encoder encodes the bit pairs into codewords which are stored and then supplied to an I-accumulator, a Q-accumulator, and a memory element. The memory element contains pre-multiplied values which are supplied to the I- and the Q-accumulators which add terms of the pre-multiplied values to form I-portions and Q-portions of a DQPSK-modulated signal. The I- and Q-portions may then be supplied to a quadrature modulator.

公开(公告)号：HUT59266A

公开(公告)日：1992-04-28

申请号：HU92190

申请日：1989-12-21

Applicant: MOTOROLA INC

Inventor： WILSON GREGORY P ,  POTRATZ BRYAN A ,  WALCZAK THOMAS J ,  MULLINS JEFFREY L

IPC: H04B7/26 ,  B21C23/08 ,  B21J5/10 ,  B21J9/04 ,  H03K5/156 ,  H04B20060101 ,  H04B3/60 ,  H04B7/00 ,  H04L5/14 ,  H04L12/40

Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when another of the bus lines is held in a logic high state.