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公开(公告)号：AU8326991A
公开(公告)日：1992-03-02
申请号：AU8326991
申请日：1991-08-02
Applicant: MOTOROLA INC
Inventor： WILSON GREGORY P , POTRATZ BRYAN A , WALCZAK THOMAS J , MULLINS JEFFERY L , PRILL MARK E
Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.
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公开(公告)号：FR2665592A1
公开(公告)日：1992-02-07
申请号：FR9110023
申请日：1991-08-06
Applicant: MOTOROLA INC
Inventor： WILSON GREGORY P , POTRATZ BRYAN A , WALCZAK THOMAS J , MULLINS JEFFERY L , PRILL MARK E
Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.
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公开(公告)号：DE4191735C2
公开(公告)日：1994-11-10
申请号：DE4191735
申请日：1991-08-02
Applicant: MOTOROLA INC
Inventor： WILSON GREGORY P , POTRATZ BRYAN A , WALCZAK THOMAS J , MULLINS JEFFERY L , PRILL MARK E
Abstract: A multiplexed synchronous/asynchronous data bus (109) is disclosed in which three bus lines (T, R, C) are used to convey bidirectional synchronous data between at least two data devices (605, 607, 609, 611) at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.
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公开(公告)号：AU629759B2
公开(公告)日：1992-10-08
申请号：AU8326991
申请日：1991-08-02
Applicant: MOTOROLA INC
Inventor： WILSON GREGORY P , POTRATZ BRYAN A , WALCZAK THOMAS J , MULLINS JEFFERY L , PRILL MARK E
Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.
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公开(公告)号：ITRM910600A1
公开(公告)日：1993-02-05
申请号：ITRM910600
申请日：1991-08-05
Applicant: MOTOROLA INC
Inventor： MULLINS JEFFREY L , POTRATZ BRYAN A , PRILL MARK E , WALCZAK THOMAS J , WILSON GREGORY P
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Patent Agency Ranking
公开(公告)号：MX9100520A
公开(公告)日：1992-04-01
申请号：MX9100520
申请日：1991-08-05
Applicant: MOTOROLA INC
Inventor： WILSON GREGORY P , POTRATZ BRYAN A , WALCZAK THOMAS J , MULLINS JEFFERY L , PRILL MARK E
Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.
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公开(公告)号：CA2124511C
公开(公告)日：1999-03-02
申请号：CA2124511
申请日：1994-05-27
Applicant: MOTOROLA INC
Inventor： TOMASI PETER A , PRILL MARK E , CAHILL STEPHEN V
Abstract: A unique method for supervising a cellular telephone call between a base station and a radio telephone of a TDMA cellular communications system includes the steps of detecting the presence of the assigned time slot (306); detecting the presence of the assigned DVCC when the assigned time slot is detected (308); incrementing a bad slot counter (316) if the assigned time slot is not detected or if the assigned DVCC is not detected; and terminating the communication (322) if the bad slot counter reaches a predetermined maximum value. A good slot counter is incremented (310) when the assigned DVCC is detected in a burst. The good slot counter is reset (318) if the assigned DVCC is not detected in the next burst, and both counters are reset (314) if the assigned DVCC is detected in consecutive bursts.
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公开(公告)号：CA2124511A1
公开(公告)日：1994-12-05
申请号：CA2124511
申请日：1994-05-27
Applicant: MOTOROLA INC
Inventor： CAHILL STEPHEN V , PRILL MARK E , TOMASI PETER A
Abstract: A unique method for supervising a cellular telephone call between a base station and a radio telephone of a TDMA cellular communications system includes the steps of determining (304) that the assigned time slot is expected to be received within a predetermined amount of time; detecting the presence of the assigned time slot (306) within the predetermined amount of time; detecting the presence of the assigned DVCC when the assigned time slot is detected (308); incrementing a bad slot counter (316) [if] responsive to the assigned time slot is not detected within the predetermined amount of time or [if] responsive to the assigned DVCC is not detected; and terminating the communication (322) [if] when the bad slot counter reaches a predetermined maximum value. A good slot counter is incremented (310) when the assigned DVCC is detected in a burst. The good slot counter is reset (318) [if] when the assigned DVCC is not detected in the next burst, and both counters are reset (314) [if] when the assigned DVCC is detected in consecutive bursts.
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公开(公告)号：BR9105818A
公开(公告)日：1992-08-25
申请号：BR9105818
申请日：1991-08-02
Applicant: MOTOROLA INC
Inventor： WILSON GREGORY P , POTRATZ BRYAN A , WALCZAK THOMAS J , MULLINS JEFFERY L , PRILL MARK E
Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.
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公开(公告)号：CA2066400C
公开(公告)日：1996-09-24
申请号：CA2066400
申请日：1991-08-02
Applicant: MOTOROLA INC
Inventor： WILSON GREGORY P , POTRATZ BRYAN A , WALCZAK THOMAS J , MULLINS JEFFERY L , PRILL MARK E
Abstract: A multiplexed synchronous/asynchronous data bus is disclosed in which three bus lines are used to convey bidirectional synchronous data between at least two data devices at a relatively low data rate. Valid half duplex asynchronous data is applied at a higher data transfer rate to one of the three bus lines when only one of the bus lines is held in a logic high state.
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