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公开(公告)号：CA814640A
公开(公告)日：1969-06-03
申请号：CA814640D
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J , MCDONALD JAMES A
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公开(公告)号：CA1249880A
公开(公告)日：1989-02-07
申请号：CA517236
申请日：1986-08-29
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J , WILLIS DONALD H , FLING RUSSELL T
Abstract: System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, tend to have jittering time bases which may cause the small image to appear jagged or tilted. This distortion in the small image may be reduced by effecting adaptive signal delays in the small picture signal responsive to the relative phase of the system clock signal with respect to the horizontal synchronizing pulses of the large and/or small picture signal. One phase measure is used to control an interpolator which combines successive samples of the small picture signal in proportions to develop sample values corresponding to samples that would have occurred had the small picture signal been sampled by a clock properly aligned to the small picture horizontal synchronizing pulses. A second phase measure is used to delay the clock signal used to recover the small picture from a memory so that the clock pulses that define the edges of the small picture occurs with the same timing relative to the large picture horizontal synchronizing pulses from line-to-line.
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公开(公告)号：FR2574240B1
公开(公告)日：1989-01-06
申请号：FR8517728
申请日：1985-11-29
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J , FLING RUSSELL THOMAS
Abstract: A television receiver/monitor includes a progressive scan processor including memories for time compressing a video input signal and doubling the line rate to reduce visible line structure when the double line-rate signal is displayed. The memories are controlled to provide a video compression factor (2.5:1) greater than the display line rate increase (2:1) to provide a display retrace time (10.8 micro-seconds) substantially equal to the blanking interval (11.0 micro-seconds) of the video input signal thereby decreasing display power losses and horizontal drive requirements.
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公开(公告)号：GB2169163B
公开(公告)日：1988-10-19
申请号：GB8531040
申请日：1985-12-17
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J
Abstract: A digital input signal to be delayed is applied to a two-point linear interpolation filter which imparts delay to the signal proportional to the value of a delay control signal. Errors in both the amplitude and the phase of the delayed signal are minimized by the addition of a correction signal to the delayed signal. The correction signal is provided by applying the input signal to a further filter and a multiplier connected in cascade. The further filter is a linear phase filter having a response zero at zero frequency and a delay equal to an add multiple of one-half of the sampling period, Ts, of the digital input signal. The multiplier is controlled so as to vary the amplitude of the compensating signal as a non-linear function of the delay control signal so as to provide maximum amplitude compensation at delays corresponding to odd multiples of Ts/2 and zero amplitude compensation at delays equal to integer multiples of Ts.
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公开(公告)号：AU8009587A
公开(公告)日：1988-04-28
申请号：AU8009587
申请日：1987-10-23
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J
Abstract: A sampled data tone control system, applicable for providing audio bass cut and boost control, includes a single variable multiplying circuit (14) for determining the system variable response characteristics. Input samples are coupled to the multiplier which has its output connected to an integrator (18,20). The integrated samples are scaled by a constant and combined with the input samples to provide tone controlled signal.
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Patent Agency Ranking
公开(公告)号：GB2190522A
公开(公告)日：1987-11-18
申请号：GB8711371
申请日：1987-05-14
Applicant: RCA CORP
Inventor： DIETERICH CHARLES BENJAMIN , CHRISTOPHER TODD J
Abstract: Circuitry for calculating the square root of a binary number iterates the equation E(K+1)=E(K)+(S-E(K)2) where E(K+1) is the current estimate of the square root of the sample S and E(K) is the previous estimate. The value E(K)2 is estimated in order to reduce the complexity of the hardware. An application is described for real time processing of digital audio signals in serial-bit format.
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公开(公告)号：DK559587D0
公开(公告)日：1987-10-26
申请号：DK559587
申请日：1987-10-26
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J
IPC: H03G5/00
Abstract: A sampled data tone control system, applicable for providing audio bass cut and boost control, includes a single variable multiplying circuit (14) for determining the system variable response characteristics. Input samples are coupled to the multiplier which has its output connected to an integrator (18,20). The integrated samples are scaled by a constant and combined with the input samples to provide tone controlled signal.
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公开(公告)号：FI874606A0
公开(公告)日：1987-10-20
申请号：FI874606
申请日：1987-10-20
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J
Abstract: A sampled data tone control system, applicable for providing audio bass cut and boost control, includes a single variable multiplying circuit (14) for determining the system variable response characteristics. Input samples are coupled to the multiplier which has its output connected to an integrator (18,20). The integrated samples are scaled by a constant and combined with the input samples to provide tone controlled signal.
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公开(公告)号：DK496087D0
公开(公告)日：1987-09-22
申请号：DK496087
申请日：1987-09-22
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J
Abstract: A sampled data treble control system, requiring a single multiplier element (22), includes the cascade connection of a first adder (20), the multiplier (22), and a second adder (24) coupled between the system input and output terminals. A subtracter (32) develops the differences between the system input and output signals and applies them to an IIR filter (26,28,30). The filtered differences are scaled and coupled to the first (20) and second adders (24). The system transfer function H(Z) is given by H(Z) = [1+(Z-1)/(1+1/A)K]/[1+(Z-1)/(1+A)K] where A is a treble control variable applied to the multiplier (22), K is a scaling constant and Z is the conventional Z-transform variable.
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公开(公告)号：FI874066A0
公开(公告)日：1987-09-17
申请号：FI874066
申请日：1987-09-17
Applicant: RCA CORP
Inventor： CHRISTOPHER TODD J
Abstract: A sampled data treble control system, requiring a single multiplier element (22), includes the cascade connection of a first adder (20), the multiplier (22), and a second adder (24) coupled between the system input and output terminals. A subtracter (32) develops the differences between the system input and output signals and applies them to an IIR filter (26,28,30). The filtered differences are scaled and coupled to the first (20) and second adders (24). The system transfer function H(Z) is given by H(Z) = [1+(Z-1)/(1+1/A)K]/[1+(Z-1)/(1+A)K] where A is a treble control variable applied to the multiplier (22), K is a scaling constant and Z is the conventional Z-transform variable.
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