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公开(公告)号：JPS6189792A
公开(公告)日：1986-05-07
申请号：JP21165184
申请日：1984-10-09
Applicant: Sony Corp
Inventor： SASE MASATOSHI
IPC: H04N9/73
Abstract: PURPOSE: To use a common detecting terminal without supplying a change-over signal from an external part, to adjust plural signal processing circuits independently and to decrease the number of external pins by adding the maximum value circuit to the signal processing circuit which generates the same output signal in the several channels and making into an integrated circuit.
CONSTITUTION: A maximum value circuit 21 is composed of three NPN typed transistors 22∼24 in which a mutual emmitter is connected to a common con stant current source 27 and respective collectors are connected to a direct current power source terminal 26. At the time of adjustment, a slider of variable resistance 28a∼30a is operated so that respective outputs of gain control circuits 2∼4 can be minimum. Next, the slider of variable resistance 28a is operated, a gain of the gain control circuit is advanced and the prescribed value is obtained while an output signal level from a detecting end is watched. Next, the slider of variable resistance 29a is operated, and in the place, where the output of the detecting end 25 exceeds the prescribed value and starts to in crease, the slider is fixed.
COPYRIGHT: (C)1986,JPO&JapioAbstract translation: 目的：为了使用公共检测端子而不提供外部转换信号，可以独立地调整多个信号处理电路，并通过将最大值电路添加到产生相同信号处理电路的方式减少外部引脚数 在多个通道中输出信号并形成集成电路。 构成：最大值电路21由三个NPN型晶体管22-24组成，其中相互发生器连接到公共恒定电流源27，并且各个集电极连接到直流电源端子26.在 调节时，操作可变电阻28a-30a的滑动器，使得增益控制电路2-4的各个输出可以是最小的。 接下来，操作可变电阻28a的滑块，增益控制电路的增益提前，并且在从监视端检测出输出信号电平的同时获得规定值。 接下来，操作可变电阻29a的滑块，并且在检测端25的输出超过规定值并开始折痕的位置处，滑块被固定。
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公开(公告)号：JPS5928769A
公开(公告)日：1984-02-15
申请号：JP13786182
申请日：1982-08-10
Applicant: Sony Corp
Inventor： YAMANAKA SEISUKE , SASE MASATOSHI , YOSHIOKA OSAMU , KAJINO ISAO
IPC: H04N5/225 , H04N5/335 , H04N5/341 , H04N5/351 , H04N5/353 , H04N5/359 , H04N5/369 , H04N5/3728 , H04N5/378 , H04N101/00
CPC classification number: H04N5/3595 , Y10S358/906
Abstract: PURPOSE: To attain still image pickup without flicker phenomenon, by reading out a picture signal for two fields' share during one frame period and making timewise picture information corresponding to an odd number field and an even number field equal with an optical shutter.
CONSTITUTION: The picture information for one frame's share read out from an image sensor 1 is recorded to a magnetic recording reproducing section 3 taking a magnetic sheet 2 as a recording medium and a recording signal is reproduced repetitively. Further, a photodetecting section of each field is interlocked with the operation of the shutter 9 and brought respectively into an effective charge storage state over at least 2-frame period. Moreover, the shutter 9 is closed until the photodetecting section of an even number field is brought into the effective charge storage state after the photodetecting section of an odd number field is brought into the effective storage state. Further, the shutter 9 is opened to provide an effective exposure period and an image pickup charge obtained at the photodetecting section of each field is read out from the sensor 1 in the state of shutter closing to obtain an image pickup output of the frame still picture.
COPYRIGHT: (C)1984,JPO&JapioAbstract translation: 目的：为了获得没有闪烁现象的静态图像拾取，通过在一个帧周期内读出两个场的共享的图像信号，并且对应于与光学快门相等的奇数场和偶数场的时间图像信息。 构成：将从图像传感器1读出的一帧共享的图像信息记录在磁记录重放部分3上，磁片2以磁片2作为记录介质并重复地重放记录信号。 此外，每个场的光电检测部分与快门9的操作互锁，并在至少2帧周期内分别进入有效的电荷存储状态。 此外，在将奇数场的光检测部分进入有效存储状态之后，快门9闭合直到偶数场的光检测部分进入有效电荷存储状态。 此外，快门9被打开以提供有效的曝光时段，并且在快门关闭的状态下从传感器1读出在每个场的光电检测部分处获得的图像拾取电荷，以获得帧静止图像的图像拾取输出 。
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公开(公告)号：JPS5884586A
公开(公告)日：1983-05-20
申请号：JP18236081
申请日：1981-11-16
Applicant: SONY CORP
Inventor： SASE MASATOSHI , ONGA MAKOTO , YAMANAKA SEISUKE
Abstract: PURPOSE:To correct the line sequence of a green pickup signal and to improve the picture quality, by summing and synthesizing a correction signal formed with a pickup charge having different color component from a mixed color component. CONSTITUTION:Since a correction signal being DELTAR' attenuating a red pickup signal (R+DELTAG) color-separated at the 2nd sample hold circuit 22 at a variable attenuator 24 is applied to a signal summing and synthesizing device 23 while a green pickup signal (G+DELTAB) receiving a mixed color being DELTAB is color-separated at the 1st sample hold circuit 21, summing and synthesizing of G+DELTAB+ DELTAR' is performed and the green pickup signal (G+DELTAB+DELTAR') is outputted. (G+ DELTAR+ DELTAB') is outputted similarly as to the green pickup signal (G+DELTAR) subjected to the mixing of DELTAR. Taking DELTAR=DELTAR', DELTAB=DELTAB', the line sequence of the green pickup signal obtained at output terminals 25 and 26 can be eliminated.
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公开(公告)号：JP2008113126A
公开(公告)日：2008-05-15
申请号：JP2006293836
申请日：2006-10-30
Inventor： KOSAKAI RYOTA , AIKI KATSUTOSHI , SATO NOBUYUKI , NAGAHAMA HIROYOSHI , SASE MASATOSHI , YONEDA YUTAKA
IPC: H04N5/232 , H04N5/225 , H04N101/00
CPC classification number: H04N9/735 , G11B27/005 , G11B27/031 , G11B31/006 , H04N5/232 , H04N5/23232 , H04N5/23245 , H04N5/23293 , H04N5/378 , H04N5/77 , H04N5/772 , H04N5/783 , H04N5/91 , H04N7/0105 , H04N7/0127 , H04N9/045 , H04N9/69 , H04N9/7904 , H04N9/80 , H04N9/87
Abstract: PROBLEM TO BE SOLVED: To enable a camera signal processing circuit to perform signal processing at a normal screen rate by eliminating the need to perform the signal processing at a high screen rate during high-speed imaging. SOLUTION: In the high-speed imaging mode, RAW data of 240 fps from an image sensor 101 are recorded in a recording device 111 through a conversion processing unit 201 and a recording device control circuit 210. The RAW data having been thinned out and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202, and an image being picked up is displayed at a display unit 112 with the signal after camera signal processing. For reproduction, the RAW data are read out of the recording device 111 at a low screen rate according to the display capability of the display unit 112, the read-out RAW data are processed by the pre-processing circuit 202 and camera signal processing circuit 203, and the display unit 112 displays a reproduced image. COPYRIGHT: (C)2008,JPO&INPIT
Abstract translation: 要解决的问题：为了使相机信号处理电路能够以高速成像方式消除在高屏幕速率下进行信号处理的需要，以正常屏幕速率进行信号处理。 解决方案：在高速成像模式中，来自图像传感器101的240fps的RAW数据通过转换处理单元201和记录装置控制电路210被记录在记录装置111中。将RAW数据变薄 通过预处理电路202向相机信号处理电路203提供输出和尺寸转换，并且在显示单元112上显示被拾取的图像与相机信号处理之后的信号。 为了再现，根据显示单元112的显示能力，RAW数据以低屏幕速率从记录装置111读出，读出的RAW数据由预处理电路202和相机信号处理电路 203，并且显示单元112显示再现的图像。 版权所有（C）2008，JPO＆INPIT
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公开(公告)号：JP2005311919A
公开(公告)日：2005-11-04
申请号：JP2004129071
申请日：2004-04-23
Applicant: Sony Corp , Texas Instr Japan Ltd , ソニー株式会社 , 日本テキサス・インスツルメンツ株式会社
Inventor： SASE MASATOSHI , AZUMA KOICHI
CPC classification number: H04N5/3575 , H04N5/361 , H04N5/3728
Abstract: PROBLEM TO BE SOLVED: To provide an optical black level adjusting circuit capable of eliminating an external capacitor by constructing the optical black level adjusting circuit with a coarse analog adjusting circuit and a precise digital adjusting circuit, and converging optical black level adjustment with several lines and easily changing a time constant by means of a digital processing.
SOLUTION: The optical black level adjusting circuit comprises: a CDS 11 for clamping an analog signal at an optical black level and sampling/holding the analog signal; an A/D converter 12 for converting the analog signal from the CDS into a digital signal; a subtracter 13 for subtracting the digital signal outputted from the A/D converter and an OB pedestal code: a subtracter 31 for subtracting the output of the subtractor 13 and an error value A; a computing element 25 for calculating a new error value A from data outputted from the subtracter 31, a predetermined coefficient and the error value A; a register 23 for storing the error value A; and a D/A converter 15 for supplying an analog voltage corresponding to the error value A as a clamp signal of the CDS 11, and the adjustment of the optical black level is accelerated without using an external capacitor.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 解决的问题：提供一种能够通过用粗略的模拟调整电路和精确的数字调节电路构成光学黑电平调节电路来消除外部电容器的光学黑电平调节电路，并且将 几行，并通过数字处理轻松地改变时间常数。 解决方案：光学黑电平调节电路包括：用于将光模拟信号钳位在光学黑电平并采样/保持模拟信号的CDS11; 用于将来自CDS的模拟信号转换为数字信号的A / D转换器12; 用于减去从A / D转换器输出的数字信号的减法器13和OB基座代码：用于减去减法器13的输出的减法器31和误差值A; 用于从减法器31输出的数据，预定系数和误差值A计算新的误差值A的计算单元25; 用于存储误差值A的寄存器23; 以及用于将对应于误差值A的模拟电压作为CDS 11的钳位信号的D / A转换器15，并且不使用外部电容器来加速光学黑电平的调整。 版权所有（C）2006，JPO＆NCIPI
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Patent Agency Ranking
公开(公告)号：JP2000041194A
公开(公告)日：2000-02-08
申请号：JP20695898
申请日：1998-07-22
Applicant: SONY CORP
Inventor： SASE MASATOSHI
IPC: H04N5/335 , H04N5/341 , H04N5/343 , H04N5/347 , H04N5/3728
Abstract: PROBLEM TO BE SOLVED: To provide the driving method of a solid-state image sensor and an image pickup device for switching an operation mode to an interlace read mode and an entire pixel read mode and picking up images. SOLUTION: The image pickup charges of entire pixels obtained by respective photosensors in each field period are read to a vertical transfer register, the image pickup charges of the entire pixels read to the vertical transfer register are transferred to a horizontal transfer register by every two horizontal lines in each horizontal scanning period and the charges for the two pixels adjacent on a vertical line are added and synthesized in the horizontal transfer register by making the combination different in an odd-numbered field and an even- numbered field. Then, the image pickup charges for the two horizontal lines added and synthesized by the horizontal transfer register are outputted as image pickup signals for one horizontal line from the horizontal transfer register through an output part by one horizontal line each in each horizontal scanning period.
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公开(公告)号：JP2000041193A
公开(公告)日：2000-02-08
申请号：JP20695498
申请日：1998-07-22
Applicant: SONY CORP
Inventor： MOTONO CHIHIRO , OKUMOTO KOJI , YOSHIHIRO TOSHITAKA , NAKATANI MASAYA , SASE MASATOSHI , TESHIROGI HIDEHIKO , YASUSATO SHIGENOBU
IPC: H04N5/232 , H04N5/335 , H04N5/341 , H04N5/347 , H04N5/372 , H04N5/77 , H04N5/782 , H04N5/907 , H04N9/79 , H04N9/804
Abstract: PROBLEM TO BE SOLVED: To provide an image pickup device capable of obtaining the still image pickup signals of high image quality by an entire pixel read mode and outputting them through an output processing means coping with an interlace read mode. SOLUTION: The image pickup signals read in the interlace read mode from a CCD image sensor 23 are supplied through a camera signal processing circuit 24 to a DV recording and reproducing signal processing part 4 as they are and the image pickup signals read in the entire pixel read mode from the CCD image sensor 23 are transformed to interlace signals by a scanning transformation part 3A and supplied to the DV recording and reproducing signal processing part 4.
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公开(公告)号：JP2517922B2
公开(公告)日：1996-07-24
申请号：JP22907386
申请日：1986-09-27
Applicant: SONY CORP
Inventor： SASE MASATOSHI
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公开(公告)号：JPH0628476B2
公开(公告)日：1994-04-13
申请号：JP12390285
申请日：1985-06-07
Applicant: SONY CORP
Inventor： KONDO NORIAKI , SASE MASATOSHI
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公开(公告)号：JPH05183912A
公开(公告)日：1993-07-23
申请号：JP26292
申请日：1992-01-06
Applicant: SONY CORP
Inventor： SASE MASATOSHI
Abstract: PURPOSE:To execute satisfactory saturation detection with simple configuration. CONSTITUTION:A signal from a CCD 1 is supplied through a sample-hold circuit 2 and an AGC circuit 3 to an A/D conversion circuit 4, and a digitized signal is supplied to a terminal 5. On the other hand, a control signal from a mu-com 6 is supplied through a D/A conversion circuit 7 to the AGC circuit 3 and supplied through a D/A conversion circuit 8 to the control part of an iris 9. Further, a signal from the A/D conversion circuit 4 is supplied to a saturation detection circuit 11. Then, the signal from the A/D conversion circuit 4 is supplied to an inverse correction circuit 12. Moreover, the control signal of the AGC circuit 3 from the mu-com 6 is supplied to the inverse correction circuit 12 and in the inverse correction circuit 12, a signal equivalent to the signal in front of the AGC circuit 3 is formed. The signal is supplied to a saturation detection circuit 12. Then, signals from the saturation detection circuits 11 and 13 are synthesized by a synthesizer circuit 14 and extracted at a control signal terminal 15 for suppressing chroma signals.
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