公开(公告)号：JPS60173853A

公开(公告)日：1985-09-07

申请号：JP2932984

申请日：1984-02-17

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/31 ,  H01L21/76

Abstract: PURPOSE:To reduce the difference in conversion from a mask by a method wherein an oxidation-resistant film is formed on an element-forming region after formation of a groove for the element isolation area on the surface of a semiconductor substrate, and the section other than the element-forming region in contact with the insulator filling the groove is partly removed; then, this section of removal is thermally oxidized. CONSTITUTION:Grooves 23 are formed in the element-forming region 22 of one main surface 21a of the substrate 21 where circuit elements are to be formed, and an SiO2 film 25 and an Si3N4 film 24 are formed over the entire surface. Next, doped oxide or SiO2 is formed as the insulator 26 so as to fill the groove 23, and further the surface is flattened by coating with a photo resist layer 27. Thereafter, etching is carried out from the surface of the resist layer 27 and stopped at the time of exposure of an oxidation-resistant mask 24. Then, the mask 24 and the film 25 on the main surface 21a in contact with the insulator 26 are removed, and etching is carried out to a depth not reaching the bottom of the groove 23. A thick SiO2 oxide layer 28 is formed by thermally oxidizing the section not coated with the mask 24. This manner enables the avoidance of generation of thermal strain due to the difference in the rate of thermal expansion from the Si substrate 21.

公开(公告)号：JPS6089932A

公开(公告)日：1985-05-20

申请号：JP19724483

申请日：1983-10-21

Applicant: SONY CORP

Inventor： KATOU TOSHIROU ,  SHIMADA TAKASHI ,  KATOU YASABUROU

IPC: H01L21/322 ,  H01L21/324

Abstract: PURPOSE:To prevent generation of a slip line due to thermal stress even if a high temperature processing is adopted by forming two layers of a protective layer formed with SiO2 and a layer of polycrystalline Si on the main surface of a semiconductor substrate. CONSTITUTION:On the first main surface 6a and the second main surface 6b of an Si wafer 6, phosphorus is diffused and an N diffusion layer 7 is formed. On the main surfaces 6a, 6b, an SiO2 film 9 is deposited. Then, a polycrystalline Si film 10 is deposited. On the other surface of the wafer 6, the layer 7 is removed by mirror polishing. After these processes, the back surface of the wafer 6 is gettered to reduce the internal defects of the wafer 6 and a heavy metal contamination, crystal defects, etc. induced during the manufacture. In this manufacture, a dual layer construction of the film 9 and the film 10 can prevent generation of a slip line due to thermal stress even a high temperature processing is used.

公开(公告)号：JPS5999742A

公开(公告)日：1984-06-08

申请号：JP20987782

申请日：1982-11-30

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/318

Abstract: PURPOSE:To improve breakdown voltage by a method wherein a substance of a composition ratio between a Si3N4 layer and a Si base body is interposed between them, stress to the Si base body side is reduced, a bird beak is made small, and the leakage currents of a junction section is minimized. CONSTITUTION:A pad layer 12 of an intermediate substance of Si and Si3N4 is applied onto the P type Si base body 11 through a CVD method, the Si3N4 film 13 is superposed and patterned, and a thick SiO2 film 14 is formed through oxidation. Since the pad 12 is of a composition between Si and Si3N4 and has comparatively compact structure, O2 does not reach to the Si base body through the pad 12, and the bird beak is made small. Since stress applied to the base body is reduced and the generation of the crystal defect of the base body is inhibited, leakage currents are little when the pad is removed and an N diffusion layer is formed, and breakdown voltage is not also lowered.

公开(公告)号：JPS57117278A

公开(公告)日：1982-07-21

申请号：JP406181

申请日：1981-01-14

Applicant: Sony Corp

Inventor： OKAZAKI NOBUMICHI ,  SHIMADA TAKASHI ,  NISHIYAMA KAZUO

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L29/78

Abstract: PURPOSE:To suppress the diffusion of metal of a metal silicide layer being weak to heat by a method wherein the heat treatment by irradiation of infrared rays is used as the heat treatment to be performed after formation of the metal silicide layer having low resistance. CONSTITUTION:A gate electrode 16G is formed on a gate insulating layer 12G, a source electrode 16S is formed coming in contact with a substrate existing at a part of a window hole 13S, and a drain electrode 16D is formed coming in contact with the substrate existing at a part of a window hole 13D respectivey. Arsenic ions 18 are implanted therein to form N type diffusion regions 17S, 17D. The semiconductor substrate 11 thereof is put in an infrared rays irradiating device, rays of the lamp are made to be irradiated on the main face of the substrate 11 implanted with ions, the heat treatment is performed at 1,000 deg.C for about 10sec to activate the ion implanted region, and the final source region 17S and the drain region 17D are formed.

Abstract translation: 目的：通过使用红外线照射的热处理作为在形成具有低电阻的金属硅化物层之后进行的热处理的方法来抑制对热弱的金属硅化物层的金属的扩散。 构成：在栅绝缘层12G上形成栅电极16G，形成与存在于窗孔13S的一部分的基板接触的源电极16S，形成与基板接触的漏电极16D 存在于窗孔13D的一部分上。 在其中注入砷离子18以形成N +型扩散区17S，17D。 将其半导体基板11放入红外线照射装置中，将灯的射线照射在注入离子的基板11的主面上，在1000℃进行热处理约10秒以激活 离子注入区域和最终源极区域17S和漏极区域17D。

公开(公告)号：JPS5649583A

公开(公告)日：1981-05-06

申请号：JP12589979

申请日：1979-09-28

Applicant: SONY CORP

Inventor： SAKAMOTO MASAMICHI ,  MATSUMOTO HIROYUKI ,  SHIMADA TAKASHI ,  HASHIMOTO TAKEO

IPC: H01L27/148 ,  H04N5/335 ,  H04N5/359 ,  H04N5/369 ,  H04N5/3728

Abstract: PURPOSE:To obtain a solid pickup element with an extra-minute pattern by the self- matching method by a method wherein the first and second masks are piled up on a semiconductor substrate, and a large window is made in the first mask, utilizing the first window of the second mask. CONSTITUTION:SiO2 and poly-Si layers 22, 23 are laid on a P type Si substrate in order. A resist mask 24 is laid over, and the mask layers 22, 23 are etched to provide the first window 25, 26, then form an N type overflow drain 2 by injecting ions. Next the mask layer 23 is excessively etched to enlarge the dimensions of the window by l1 so as to make the second window 27. After the resist 24 has been removed, ions are injected from the window 27 of the poly-Si 23, with their density being selected, to make a P type overflow control gate layer 4 and a channel stopper 5 on the both side of the drain 2. After this, a CCD interline type image pickup element is formed by means of the ordinary process. With such a constitution as this, layers 2, 4, 5 are formed in self-matching, making necessary the mask-matching only once while liquidating a shear in masking. Using the excessive etching method, the length 11 of the control gate channel can be regularized, so that a solid pickup element with an extra-minute pattern can be obtained.

公开(公告)号：JPS55160469A

公开(公告)日：1980-12-13

申请号：JP6820079

申请日：1979-05-31

Applicant: SONY CORP

Inventor： HIRATA YOSHIMI ,  SHIMADA TAKASHI

IPC: H01L27/092 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/78

Abstract: PURPOSE:To form source and drain regions having necessary high density impurity in the semiconductor device by doping impurity with a gate electrode laminated with low specific resistance semiconductor layer and metallic layer and polyimide series resin mask layer as masks. CONSTITUTION:Openings 2a, 2b are formed at a thick insulating layer 2 on an N type semiconductor substrate 1, and P type region 3 is formed in the substrate 1. The low specific resistance semicodnctor layer 5 and the metallic layer 20 are laminated through a gate insulating layer 4 on a gate electrode are coated in the openings 2a, 2b. Then, polyimide series resin mask layer 21 is selectively coated on the opening 2a. Thereafter, with the layers 2, 5, 21 as masks a P type impurity is injected to the substrate 1 to form source and drain regions 7s, 7d. Subsequently, the layer 21 is removed, and a layer 21 is formed on the opening 2b. Then, with the layers 2, 5, 21 as masks N type impurity is injected into the region 3 to form source and drain regions 8s, 8d. In this manner, necessary high density can be formed as the source and the drain regions, and exact self-alignment can be carried out thereat.

公开(公告)号：JPS55141748A

公开(公告)日：1980-11-05

申请号：JP4931379

申请日：1979-04-20

Applicant: SONY CORP

Inventor： YAMOTO HISAYOSHI ,  MATSUSHITA TAKESHI ,  OOTSU KOUJI ,  SHIMADA TAKASHI ,  SHIBAZAKI MITSURU ,  TAKAKUWA HIDEMI

IPC: H01L27/04 ,  H01B1/04 ,  H01L21/822 ,  H01L27/06 ,  H01L29/78

Abstract: PURPOSE:To enable to control the resistivity of a resistor film of a MOSFET by oxygen concentration and to uniformly control thereof in high accuracy by varying the oxygen concentration in the state that the impurity density in a silicon layer is set higher than the vicinity of the saturating point. CONSTITUTION:An n-type source region 2 and a drain region 3 are formed in a p-type semiconductor substrate 1, a thin resistor film 5 becoming a loading resistor of a MOSFET is formed at predetermined position on a silicon film 4 of the substrate 1. When forming the silicon layer 4, a thin film resistor 5 for the MOSFET is formed by varying the oxygen concentration in the layer 4 in the state that the impurity density in the layer 4 is set higher than the vicinity of the saturating point and then controlling the resistivity of the layer 4 to desired value by a heat treatment.

公开(公告)号：JPS54105979A

公开(公告)日：1979-08-20

申请号：JP1272878

申请日：1978-02-07

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  OOTSU KOUJI ,  MOCHIZUKI HIDENOBU

IPC: H01L21/8234 ,  H01L21/8247 ,  H01L27/088 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To reduce the photoethcing processes as well as to lower the reading voltage of the memory by forming the MOSFET and MNOSFET memory elements on the same semiconductor substrate through the self-alignment method. CONSTITUTION:N-type island region 42a to form FET and N-type island region 42b are formed through diffusion on P-type Si substrate 41, and the entier surface is covered with insulator film 43. Then film 43 is removed on region 42a and 42b to coat newly thin SiO2 film 34, and poly-crystal Si layer 35 containing the impurity is grown on film 34 with openings 46 49 drilled via the photoetching. After this, P-type source and drain regions 40s, 40d, 30s and 30d are formed through diffusion with use of these openings at region 42a and 42d. Furthermore, opening 51 enclosed by region 30s and 30d is provided at region 42b to be covered with SiO2 film 31. Then the entire surface is covered with SiO2 film 32 with the opening drilled at each region, and then electrode 53s, 53d, 54s and 54d are attached each.

公开(公告)号：JPS5324280A

公开(公告)日：1978-03-06

申请号：JP9902876

申请日：1976-08-19

Applicant: SONY CORP

Inventor： OOTSU KOUJI ,  MOCHIZUKI HIDENOBU ,  SUZUKI KAZUO ,  SHIMADA TAKASHI

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/78

Abstract: PURPOSE:To make an IC of IG type MOSFETs by making insulation layers having thick and thin parts with the same mask, and opening holes through the use of the difference in film thickness thereby forming the diffusion mask.

公开(公告)号：JPS52117581A

公开(公告)日：1977-10-03

申请号：JP3491776

申请日：1976-03-30

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L29/78

Abstract: PURPOSE:To enable higher inverse voltage between the gate and drain and to stabilize the second channel, by providing the intermediate domain of high impurity density with the same conductive type as the source and drain domain and not subjected to external electric field, between the first and second channel under the gate insulation.