82.
    发明专利
    未知

    公开(公告)号:FR2792135B1

    公开(公告)日:2001-11-02

    申请号:FR9904548

    申请日:1999-04-07

    Abstract: The coupling between transponder and terminal is reduced by altering the resonant frequency of either the terminal or transponder coupling circuits when the two are in close proximity. When the coupling is reduced, the data rate for the communication between terminal and transponder is automatically increased, which can be achieved because the coupling is effectively a transformer coupling.

    83.
    发明专利
    未知

    公开(公告)号:FR2792132B1

    公开(公告)日:2001-11-02

    申请号:FR9904544

    申请日:1999-04-07

    Abstract: The terminal (1) uses inductive coupling to read from and write to a transponder, and includes a resonant circuit (Li,Ci) tuned to receive an AC HF excitation voltage. The resonant frequency may be altered so as to detune the LC in the event that a transponder is very close to the terminal. A capacitor (24) may be controlled by a control circuit (21) and with impedance (Li) to detect a gap of phase in relation to the signal of REF reference and to modify the capacity Ci of the capacitor (24). An Independent claim is included for a contactless system of data transmission.

    84.
    发明专利
    未知

    公开(公告)号:FR2804557A1

    公开(公告)日:2001-08-03

    申请号:FR0001214

    申请日:2000-01-31

    Inventor: WUIDART LUC

    Abstract: A terminal for generating an electromagnetic field adapted to cooperating with at least one transponder when the latter enters its field and including an oscillating circuit adapted to receiving a high-frequency A.C. excitation voltage, circuitry for regulating the signal phase in the oscillating circuit with respect to a reference value, circuitry for determining an instantaneous information relative to the magnetic coupling between the transponder and the terminal, and circuitry for adapting the electromagnetic field power according to at least said present information.

    85.
    发明专利
    未知

    公开(公告)号:FR2787655B1

    公开(公告)日:2001-03-09

    申请号:FR9816383

    申请日:1998-12-21

    Abstract: The transponder is of the type having an oscillating circuit (L2,C2) in front of a rectifier circuit (13) designed to produce a continuous voltage (Va) to an electronic circuit (17). The circuit (17) includes means for emitting digital data codes. The transponder has two capacitive modulation circuits (C2,K1; C4,K2) respectively associated with each end terminal of an inductive part (L2) of the oscillating circuit. A reference terminal of each modulating circuit is connected to a reference voltage (15) of the electronic circuit supply

    86.
    发明专利
    未知

    公开(公告)号:DE69610456T2

    公开(公告)日:2001-02-08

    申请号:DE69610456

    申请日:1996-05-06

    Abstract: The rectifying process involves utilising a number of capacitors (C1,C2) of progressively decreasing value, connected across a rectifier output, in series with resistors (R1,R2) of progressively decreasing value. The discharge of these capacitors is blocked during the initial phase of the fall in the AC voltage applied to the rectifier (D1-D4) after the maximum of the cycle. The duration of the blocking of the capacitors is longer for the smaller value capacitors. As soon as a capacitor is unblocked and can discharge the currently discharging capacitor is blocked. The timing is controlled by comparison of the potential across the DC rails at each stage with a set reference value.

    87.
    发明专利
    未知

    公开(公告)号:DE69610456D1

    公开(公告)日:2000-11-02

    申请号:DE69610456

    申请日:1996-05-06

    Abstract: The rectifying process involves utilising a number of capacitors (C1,C2) of progressively decreasing value, connected across a rectifier output, in series with resistors (R1,R2) of progressively decreasing value. The discharge of these capacitors is blocked during the initial phase of the fall in the AC voltage applied to the rectifier (D1-D4) after the maximum of the cycle. The duration of the blocking of the capacitors is longer for the smaller value capacitors. As soon as a capacitor is unblocked and can discharge the currently discharging capacitor is blocked. The timing is controlled by comparison of the potential across the DC rails at each stage with a set reference value.

    88.
    发明专利
    未知

    公开(公告)号:AT196702T

    公开(公告)日:2000-10-15

    申请号:AT96410045

    申请日:1996-05-06

    Abstract: The rectifying process involves utilising a number of capacitors (C1,C2) of progressively decreasing value, connected across a rectifier output, in series with resistors (R1,R2) of progressively decreasing value. The discharge of these capacitors is blocked during the initial phase of the fall in the AC voltage applied to the rectifier (D1-D4) after the maximum of the cycle. The duration of the blocking of the capacitors is longer for the smaller value capacitors. As soon as a capacitor is unblocked and can discharge the currently discharging capacitor is blocked. The timing is controlled by comparison of the potential across the DC rails at each stage with a set reference value.

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