公开(公告)号：WO2006021726A3

公开(公告)日：2007-10-04

申请号：PCT/FR2005050646

申请日：2005-08-04

Applicant: ST MICROELECTRONICS SA ,  BAILLY ALAIN

Inventor： BAILLY ALAIN

IPC: H02M3/335 ,  H02M1/00 ,  H02M1/32

CPC classification number: H02M3/33523 ,  H02M1/32

Abstract: The invention concerns a circuit (30) for detecting an overload in a load supplied by a switched-mode power supply, comprising: a first comparator (25) of a first voltage based on the supply voltage of the load relative to a first threshold (V FB ), supplying a regulating signal (CT) to a pulse generator (6) controlling the switched-mode power supply; a second comparator (31) of a second voltage relative to a second threshold (V OLV ), supplying a signal (OVL) indicating the presence of an overload; and means (C33, 34, 35, M35) for automatically controlling said second voltage by a third threshold (V INI ) lower than the second and higher than the first, and for deactivating the second comparator as long as said automatic control is maintained.

Abstract translation: 本发明涉及一种用于检测由开关模式电源提供的负载中的过载的电路（30），包括：基于负载的电源电压相对于第一阈值的第一电压的第一比较器（25） 将调节信号（CT）提供给控制开关模式电源的脉冲发生器（6）; 相对于第二阈值（V SB OLV ）的第二电压的第二比较器（31），提供指示存在过载的信号（OVL）; 以及用于将所述第二电压自动控制低于第二阈值并且高于第一阈值的第三阈值（V SB INI ）并且用于长时间停用第二比较器的装置（C33,34,35，M35） 如所述自动控制被维护。

公开(公告)号：FR2874138A1

公开(公告)日：2006-02-10

申请号：FR0451806

申请日：2004-08-06

Applicant: ST MICROELECTRONICS SA

Inventor： BAILLY ALAIN

IPC: H02M1/08 ,  G05F1/10 ,  H02M1/00 ,  H02M1/32 ,  H02M3/335

Abstract: L'invention concerne un circuit (30) de détection d'une surcharge dans une charge alimentée par une alimentation à découpage, comprenant : un premier comparateur (25) d'une première tension fonction de la tension d'alimentation de la charge par rapport à un premier seuil (VFB) , fournissant un signal (CT) de régulation à un générateur (6) d'impulsions de commande de l'alimentation à découpage ; un deuxième comparateur (31) d'une deuxième tension par rapport à un deuxième seuil (VOVL) , fournissant un signal (OVL) indicateur de la présence d'une surcharge ; et des moyens (C33, 34, 35, M35) pour asservir ladite deuxième tension sur un troisième seuil (VINI) inférieur au deuxième et supérieur au premier, et pour désactiver le deuxième comparateur tant que cet asservissement est maintenu.

公开(公告)号：DE69808043T2

公开(公告)日：2003-08-14

申请号：DE69808043

申请日：1998-02-10

Applicant: ST MICROELECTRONICS SA

Inventor： BAILLY ALAIN

IPC: H05B41/282

公开(公告)号：DE69718388D1

公开(公告)日：2003-02-20

申请号：DE69718388

申请日：1997-07-24

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  BAILLY ALAIN

IPC: H02M3/335 ,  H02M7/06

Abstract: The supply unit is designed to supply a first high voltage and a second low voltage. The source for the first voltage includes a first capacitor(C1;C2) which receives a voltage from a rectifier. The first capacitor is connected in series with a DC low voltage source including in parallel: - a first diode(Da) in series with a second capacitor(Ca), - a rectifier(D) of opposite polarity to that of the first diode, and, - a voltage limiter(12) of the feedback type, the terminals(B,G) of the DC low voltage source correspond to the terminals of the second capacitor. The voltage limiter consists of a thyristor(Th) whose trigger and anode are connected by a Zener diode(Z). The unit also uses a current limiter(R) in series with the voltages sources.

公开(公告)号：FR2815196A1

公开(公告)日：2002-04-12

申请号：FR0012809

申请日：2000-10-06

Applicant: ST MICROELECTRONICS SA

Inventor： BAILLY ALAIN ,  ESTEVE LIONEL

IPC: G05F1/565 ,  H02M3/156 ,  H03F3/45 ,  H03H5/02 ,  H03K7/08

Abstract: The error amplifier comprises an operational amplifier (1') whose output controls an active load (10), which is a MOS transistor, for discharging a resistive-capacitive network (R4,C4) connected to a reference-current (Iref) source (12), and resistors (R5,R6) connected so to recopy the reference current into an input resistor (R). The input node (6') receives a measured or controlled signal (Vreg), and the error signal (Ve) is available on the nodes of the resistive-capacitive network. The transfer function is tuned by the resistive and capacitive values (R4,C4). The inputs of operational amplifier are each connected by a resistor (R5,R6) to a reference potential, which is the ground node (7) potential. The first power node (11) of active load is also the output node and is connected by the intermediary of the reference-current source (12) to the supply voltage (Vdd), and the second power node (13) is connected to one input of the operational amplifier; the other input is connected to the anode (4') dividing the input voltage according to the values of resistances (R,R6). The resistive-capacitive network comprises a resistor (R4) connected in parallel with a capacitor (C4) between the output node and the ground. The error amplifier is implemented in the form of an integrated circuit wherein all resistances and capacitances are integrated with the operational amplifier except the input resistor (R).

公开(公告)号：DE69602885T2

公开(公告)日：1999-10-07

申请号：DE69602885

申请日：1996-04-26

Applicant: ST MICROELECTRONICS SA

Inventor： NICOLAI JEAN ,  BAILLY ALAIN

IPC: H02P29/00 ,  H02P25/14 ,  H02P7/638

公开(公告)号：DE60025635D1

公开(公告)日：2006-04-06

申请号：DE60025635

申请日：2000-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： BAILLY ALAIN ,  BARRET JEAN

IPC: H02M3/28 ,  H02M3/335 ,  H03K17/082

Abstract: The invention concerns a control circuit ( 20 ) of a switch ( 6 ) chopping a voltage supply of a primary winding of a power converter transformer, comprising means ( 45 ) for detecting the current in the switch in closed state after a predetermined time following each closure of said switch, and a comparator ( 40 ) of said current relative to a threshold (Ilim), the result of said comparator being taken into account for a predetermined time interval close to the beginning of a closing cycle of said chopping switch.

公开(公告)号：FR2816128A1

公开(公告)日：2002-05-03

申请号：FR0014015

申请日：2000-10-31

Applicant: ST MICROELECTRONICS SA

Inventor： BAILLY ALAIN

IPC: H02M3/335 ,  H02M3/28

Abstract: A unit (21) consisting of a resistive and capacitive network measures the average value of the voltage (Vaux) at the terminals of the auxiliary winding at the end of its demagnetization period. The units time constant is low before the control pulse period of the switch (6). The unit receives the voltage (Vaux) from the auxiliary winding only during demagnetization periods of the secondary winding (7). The voltage converter has a switch (6) control circuit (11). The switch connects a current supply to a primary winding (5) of a transformer (4). One of the transformers secondary windings (7) is connected to a capacitor (C2) which provides a continuous regulated output voltage (Vout). An auxiliary winding (8) of transformer provides a voltage supply to the control circuit. Sensors (23,24) detect the demagnetization periods of the auxiliary winding (8).

公开(公告)号：DE69803341D1

公开(公告)日：2002-02-28

申请号：DE69803341

申请日：1998-06-19

Applicant: ST MICROELECTRONICS SA

Inventor： BAILLY ALAIN

IPC: H02M1/00 ,  H02M1/42 ,  H02M1/12 ,  H02M7/06

Abstract: A smoothing capacitor (C1) for a load (L) supplied from a full-wave rectified (1) AC source (XY) is provided with two different current paths. While the capacitor discharges into the load its current passes via a diode (D1), at other times during each voltage half-cycle the load current is provided by the rectifier, which simultaneously recharges the capacitor via a current source (10) based on an MOS transistor. The diode, which is incorporated in the transistor, is non-conducting under these conditions. The transistor is controlled by a comparator (11) having as one input (13) a set value for the time of conduction of the current source, as the other (12) a signal representing the charging periods of the capacitor.

公开(公告)号：DE69610456T2

公开(公告)日：2001-02-08

申请号：DE69610456

申请日：1996-05-06

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  BAILLY ALAIN

IPC: H02M1/00 ,  H02M1/42 ,  H02M1/12 ,  H05B41/295

Abstract: The rectifying process involves utilising a number of capacitors (C1,C2) of progressively decreasing value, connected across a rectifier output, in series with resistors (R1,R2) of progressively decreasing value. The discharge of these capacitors is blocked during the initial phase of the fall in the AC voltage applied to the rectifier (D1-D4) after the maximum of the cycle. The duration of the blocking of the capacitors is longer for the smaller value capacitors. As soon as a capacitor is unblocked and can discharge the currently discharging capacitor is blocked. The timing is controlled by comparison of the potential across the DC rails at each stage with a set reference value.