-
公开(公告)号：US20220165909A1
公开(公告)日：2022-05-26
申请号：US17667575
申请日：2022-02-09
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur
IPC: H01L33/00 , H01L33/32 , H01L31/0352 , H01L33/14 , H01L31/105 , H01L31/0224 , H01L31/0304 , H01L33/02 , H01L31/109 , H01L33/04
Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The heterostructure can include a p-type interlayer located between the electron blocking layer and the p-type contact layer. In an embodiment, the electron blocking layer can have a region of graded transition. The p-type interlayer can also include a region of graded transition.
-
公开(公告)号：US10923623B2
公开(公告)日：2021-02-16
申请号：US16299362
申请日：2019-03-12
Applicant: Sensor Electronic Technology, Inc.
Inventor： Michael Shur , Rakesh Jain , Maxim S. Shatalov , Alexander Dobrinsky , Jinwei Yang , Remigijus Gaska , Mikhail Gaevski
IPC: H01L33/06 , H01L33/18 , H01L33/38 , H01L33/00 , H01S5/022 , H01S5/343 , H01L33/30 , H01S5/32 , H01S5/34
Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
-
公开(公告)号：US10903391B2
公开(公告)日：2021-01-26
申请号：US16442990
申请日：2019-06-17
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur
IPC: H01L33/00 , H01L33/32 , H01L31/0352 , H01L33/14 , H01L31/105 , H01L31/0224 , H01L31/0304 , H01L33/02 , H01L31/109 , H01L33/04 , H01L33/06
Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
-
公开(公告)号：US10535793B2
公开(公告)日：2020-01-14
申请号：US15602677
申请日：2017-05-23
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Maxim S. Shatalov , Jinwei Yang , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.
-
公开(公告)号：US10069034B2
公开(公告)日：2018-09-04
申请号：US15588896
申请日：2017-05-08
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Maxim S. Shatalov , Jinwei Yang , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L33/00 , H01L33/14 , H01L33/04 , H01L31/0224 , H01L31/0352 , H01L31/105 , H01L33/32
CPC classification number: H01L33/002 , H01L31/022408 , H01L31/035236 , H01L31/105 , H01L33/0062 , H01L33/025 , H01L33/04 , H01L33/145 , H01L33/32 , H01L2933/0008
Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.
-
Patent Agency Ranking
公开(公告)号：US20170338371A1
公开(公告)日：2017-11-23
申请号：US15660191
申请日：2017-07-26
Applicant: Sensor Electronic Technology, Inc.
Inventor： Daniel Billingsley , Robert M. Kennedy , Wenhong Sun , Rakesh Jain , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/0025 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/12 , H01L33/20 , H01L33/24 , H01L33/32 , H01L2224/16225
Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
-
公开(公告)号：US20170256672A1
公开(公告)日：2017-09-07
申请号：US15602677
申请日：2017-05-23
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Maxim S. Shatalov , Jinwei Yang , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/0025 , H01L33/007 , H01L33/0075 , H01L33/04 , H01L33/06 , H01L33/12 , H01L33/145 , H01L33/32
Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.
-
公开(公告)号：US09735315B2
公开(公告)日：2017-08-15
申请号：US15265975
申请日：2016-09-15
Applicant: Sensor Electronic Technology, Inc.
Inventor： Daniel Billingsley , Robert M. Kennedy , Wenhong Sun , Rakesh Jain , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC: H01L29/06 , H01L33/12 , H01L33/32 , H01L33/00 , H01L21/02 , H01L29/15 , H01L29/20 , H01L33/20 , H01L33/24 , H01L33/06
CPC classification number: H01L33/12 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L29/155 , H01L29/2003 , H01L33/0025 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/20 , H01L33/24 , H01L33/32 , H01L2224/16225
Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
-
公开(公告)号：US09660133B2
公开(公告)日：2017-05-23
申请号：US14493388
申请日：2014-09-23
Applicant: Sensor Electronic Technology, Inc.
Inventor： Rakesh Jain , Maxim S. Shatalov , Jinwei Yang , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
CPC classification number: H01L33/0025 , H01L33/007 , H01L33/0075 , H01L33/04 , H01L33/06 , H01L33/12 , H01L33/145 , H01L33/32
Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.
-
公开(公告)号：US20160211331A1
公开(公告)日：2016-07-21
申请号：US15083423
申请日：2016-03-29
Applicant: Sensor Electronic Technology, Inc.
Inventor： Maxim S. Shatalov , Jinwei Yang , Wenhong Sun , Rakesh Jain , Michael Shur , Remigijus Gaska
IPC: H01L29/15 , H01L29/20 , H01L29/06 , H01L29/205
CPC classification number: H01L29/158 , H01L21/0237 , H01L21/02458 , H01L21/02505 , H01L21/02507 , H01L21/02513 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L33/007 , H01L33/12
Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
Abstract translation: 提供了诸如III族氮化物基半导体结构的半导体结构。 半导体结构包括含有半导体层的空腔。 含腔的半导体层可以具有大于两个单层和多个空腔的厚度。 空腔可以具有至少一纳米的特征尺寸和至少五纳米的特征分离。
-
-
-
-
-
-
-
-
-
Search Results
95
records
(took 0.042 seconds)
