公开(公告)号：US20160172308A1

公开(公告)日：2016-06-16

申请号：US15052508

申请日：2016-02-24

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Yi-Ting Chen

IPC: H01L23/544 ,  H01L21/033 ,  H01L23/532

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L23/53271 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract translation: 描述了应用于包括第一光刻步骤，第一蚀刻步骤，第二光刻步骤和第二蚀刻步骤的LELE型双重图案化光刻（DPL）工艺的覆盖标记。 覆盖标记包括由第一光刻步骤限定的当前层的先前层，第二x方向和y方向图案的第一x方向图案和第一y方向图案，以及第三x方向和y方向图案， 由第二光刻步骤限定的当前层的方向图案。 第二x方向图案和第三x方向图案交替排列在第一x方向图案旁边。 第二y方向图案和第三y方向图案交替排列在第一y方向图案旁边。

公开(公告)号：US20160163532A1

公开(公告)日：2016-06-09

申请号：US14562768

申请日：2014-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chieh-Te Chen

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0206 ,  H01L21/02186 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N2 and O2.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成硬掩模; 在硬掩模上形成第一图案化掩模层; 使用第一图案化掩模层去除用于形成图案化硬掩模的硬掩模的一部分; 并且利用气体剥离第一图案化掩模层，同时在图案化的硬掩模上形成保护层，其中气体选自N2和O2。

公开(公告)号：US09349607B1

公开(公告)日：2016-05-24

申请号：US14792630

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/0273 ,  H01L21/3086

Abstract: A method of forming a line pattern including following steps. First of all, a substrate having a first region and a second region is provided. Next, a directed self-assembly (DSA) material layer is formed on the substrate, covering the first region and the second region. Then, the DSA material layer in the second region is removed, to form a patterned DSA material layer. After these, an annealing process is performed to enable only the DSA material layer in the first region and to form a plurality of first stripe structures and a plurality of second stripe structures arranged alternately in a first direction.

Abstract translation: 一种形成包括以下步骤的线条图案的方法。 首先，提供具有第一区域和第二区域的基板。 接下来，在衬底上形成定向自组装（DSA）材料层，覆盖第一区域和第二区域。 然后，去除第二区域中的DSA材料层，以形成图案化的DSA材料层。 之后，进行退火处理，以仅使第一区域中的DSA材料层能够形成多个第一条纹结构和沿第一方向交替布置的多个第二条纹结构。

公开(公告)号：US09337260B2

公开(公告)日：2016-05-10

申请号：US14549559

申请日：2014-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.

Abstract translation: 半导体结构包括在基板中的多个第一绝缘体，围绕所述基板中的所述第一绝缘体的侧壁和底部的公共绝缘层，以及在所述公共绝缘层上的所述基板的悬置部分。

公开(公告)号：US20160126194A1

公开(公告)日：2016-05-05

申请号：US14533108

申请日：2014-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Teng-Chin Kuo ,  En-Chiuan Liou

IPC: H01L23/544 ,  H01L21/311 ,  G01B11/00

CPC classification number: H01L21/311 ,  G01B11/002 ,  G03F7/70633 ,  G03F7/70683

Abstract: The present invention provides a measurement mark structure, including a plurality of inner patterns, the inner patterns being arranged along a first direction, and an outer pattern, positioned surrounding the inner patterns, and the outer pattern is rectangular frame shaped.

Abstract translation: 本发明提供一种测量标记结构，包括多个内部图案，内部图案沿着第一方向布置，外部图案位于围绕内部图案的位置，外部图案是矩形框形。

公开(公告)号：US20160093573A1

公开(公告)日：2016-03-31

申请号：US14498217

申请日：2014-09-26

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Yi-Ting Chen

IPC: H01L23/544 ,  H01L21/66 ,  H01L21/311 ,  H01L21/033 ,  H01L23/532 ,  H01L21/027

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L23/53271 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract translation: 描述了应用于包括第一光刻步骤，第一蚀刻步骤，第二光刻步骤和第二蚀刻步骤的LELE型双重图案化光刻（DPL）工艺的覆盖标记。 覆盖标记包括由第一光刻步骤限定的当前层的先前层，第二x方向和y方向图案的第一x方向图案和第一y方向图案，以及第三x方向和y方向图案， 由第二光刻步骤限定的当前层的方向图案。 第二x方向图案和第三x方向图案交替排列在第一x方向图案旁边。 第二y方向图案和第三y方向图案交替排列在第一y方向图案旁边。

公开(公告)号：US20150276382A1

公开(公告)日：2015-10-01

申请号：US14226834

申请日：2014-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Kuei-Chun Hung ,  Chun-Chi Yu

IPC: G01B11/14 ,  G01B11/28

CPC classification number: G03F9/7076

Abstract: A measurement mark structure includes a mark pattern and a pair of assistant bars positioned at two opposite sides of the mark pattern. The mark pattern includes a plurality of segments. The segments of the mark pattern are arranged along a first direction and the pair of the assistant bars are expend along the first direction.

Abstract translation: 测量标记结构包括标记图案和位于标记图案的两个相对侧的一对辅助条。 标记图案包括多个片段。 标记图案的区段沿着第一方向布置，并且一对辅助条沿着第一方向消耗。

公开(公告)号：US08921226B2

公开(公告)日：2014-12-30

申请号：US13740289

申请日：2013-01-14

Applicant: United Microelectronics Corp.

Inventor： Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang ,  Po-Chao Tsao

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76855 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Abstract translation: 形成至少具有接触插塞的半导体结构的方法包括以下步骤。 首先，在衬底上形成至少一个晶体管和层间电介质（ILD）层，并且晶体管包括栅极结构和两个源极/漏极区域。 随后，在ILD层和晶体管上形成覆盖层，并且形成穿过覆盖层和ILD层的多个开口直到到达源/漏区。 之后，形成导电层以覆盖盖层并填充开口，并且进一步去除导电层的一部分以形成多个第一接触塞，其中剩余导电层的顶表面和顶表面 剩余的盖层是共面的，剩余的盖层完全覆盖栅极结构的顶表面。

公开(公告)号：US20240345469A1

公开(公告)日：2024-10-17

申请号：US18308670

申请日：2023-04-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Chen Sun ,  En-Chiuan Liou ,  Song-Yi Lin

IPC: G03F1/38

CPC classification number: G03F1/38 ,  H01L21/0273

Abstract: A photomask structure including a layout pattern, a first L-type assist pattern, and a second L-type assist pattern is provided. An end portion of the layout pattern includes a first edge, a second edge, and a third edge. The second edge is connected to one end of the first edge, and the third edge is connected to another end of the first edge. The first L-type assist pattern is located between the second L-type assist pattern and the first edge. The layout pattern, the first L-type assist pattern, and the second L-type assist pattern are separated from each other. The first L-type assist pattern surrounds the first edge and the second edge. The second L-type assist pattern surrounds the first edge and the third edge.

公开(公告)号：US20210074832A1

公开(公告)日：2021-03-11

申请号：US16951361

申请日：2020-11-18

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092

Abstract: Provided is a manufacturing method of s semiconductor structure. The method includes: providing a substrate, wherein the substrate has a plurality of fin portions and at least one recessed portion, the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions; forming a doping layer on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion; and forming a dielectric layer on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.