公开(公告)号：US20200027985A1

公开(公告)日：2020-01-23

申请号：US16109714

申请日：2018-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chih-Wei Su ,  Je-Min Wen

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/764

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.

公开(公告)号：US10347712B1

公开(公告)日：2019-07-09

申请号：US15893715

申请日：2018-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/06 ,  H01L21/762 ,  H01L23/522 ,  H01L21/763

CPC classification number: H01L29/0607 ,  H01L21/762 ,  H01L21/763 ,  H01L23/5225

Abstract: A method for fabricating semiconductor device includes: forming a metal-oxide semiconductor (MOS) transistor on a substrate; forming a first interlayer dielectric (ILD) layer on the MOS transistor; removing part of the first ILD layer to form a trench adjacent to the MOS transistor; forming a trap rich structure in the trench; forming a second ILD layer on the MOS transistor and the trap rich structure; forming a contact plug in the first ILD layer and the second ILD layer and electrically connected to the MOS transistor; and forming a metal interconnection on the second ILD layer and electrically connected to the contact plug.

公开(公告)号：US12300534B2

公开(公告)日：2025-05-13

申请号：US17880685

申请日：2022-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Chee Hau Ng ,  Ching-Yang Wen ,  Purakh Raj Verma

IPC: H01L21/762 ,  H01L21/304 ,  H01L21/768

Abstract: A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.

公开(公告)号：US12131976B2

公开(公告)日：2024-10-29

申请号：US17037542

申请日：2020-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/36 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/485 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/3677 ,  H01L21/76898 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/485 ,  H01L24/08 ,  H01L24/32 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.

公开(公告)号：US12080622B2

公开(公告)日：2024-09-03

申请号：US18136329

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Purakh Raj Verma ,  Ching-Yang Wen ,  Chee Hau Ng

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/3735 ,  H01L21/4871 ,  H01L23/15 ,  H01L23/3736

Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

公开(公告)号：US20240162093A1

公开(公告)日：2024-05-16

申请号：US18080688

申请日：2022-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Chun Chang ,  Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes first providing a substrate having a core region, a LNA region, a I/O region, and a PA region, forming a first gate structure on the LNA region, a second gate structure on the PA region, a third gate structure on the core region, and a fourth gate structure on the I/O region, forming an interlayer dielectric (ILD) layer on the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure, and then forming a first hard mask on the first gate structure and a second hard mask on the second gate structure. Preferably, a width of the first hard mask is greater than a width of the first gate structure.

公开(公告)号：US20240136312A1

公开(公告)日：2024-04-25

申请号：US17989633

申请日：2022-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  XINGXING CHEN

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/16 ,  H01L25/16 ,  H01L27/1203 ,  H01L28/90 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

公开(公告)号：US20240038832A1

公开(公告)日：2024-02-01

申请号：US17892116

申请日：2022-08-21

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  Chee-Hau Ng ,  Chin-Wei Ho

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.

公开(公告)号：US11848253B2

公开(公告)日：2023-12-19

申请号：US17521805

申请日：2021-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L23/4821 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/7682 ,  H01L21/76243 ,  H01L23/485

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

公开(公告)号：US20230230938A1

公开(公告)日：2023-07-20

申请号：US18123317

申请日：2023-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/58 ,  H01L21/71 ,  H01L21/56

CPC classification number: H01L23/585 ,  H01L21/71 ,  H01L21/56

Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.