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公开(公告)号：EP1650890B1
公开(公告)日：2012-04-18
申请号：EP03817647.5
申请日：2003-07-25
Applicant: FUJITSU LIMITED
CPC classification number: H03G3/3052 , H03G3/005 , H03G3/3078 , H03G3/3089 , H03G2201/103 , H03G2201/202 , H03G2201/305 , H04B1/707 , H04B2201/70701 , H04B2201/70706
Abstract: A received frame is branched into a gain control system (20A) for common pilot signals and a gain control system (20B) for individual data signals. The gain control system (20A) controls the gain of the common pilot signals, and the gain control system (20B) controls the gain of the data signals. A signal processor (30) establishes synchronization of frames, outputs a gain control signal (g1) so that the gain of the common pilot signal is constant, to a gain control circuit (21a) for the common pilot signals, and outputs a gain control signal (g2) so that the gain of the data signal is constant, to a gain control circuit (21b) for the data signals. The gain is controlled to be constant, thereby preventing saturation of ADC (26a, 26b, 27a, 27b) and S/N deterioration.
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公开(公告)号：EP1886313A1
公开(公告)日：2008-02-13
申请号：EP06771815.5
申请日：2006-06-01
Applicant: ZORAN CORPORATION
Inventor： HADDAD, Bassel
CPC classification number: H03G3/001 , H03G3/3052 , H03G2201/202
Abstract: An automatic gain control (AGC) controls the signal amplitude at the input to an analog to digital converter (ADC) input by applying a gain that produces a desired overall amplitude resolution of the patterns actually presented by the signal delivered by the ADC converter. Short RLL patterns will have sufficient resolution for reliable extraction as a result of having sufficient overall amplitude, which thereby strengthens the ability of the read channel to correctly extract data. Moreover, the system determines correct AGC settings responsive to measurements of user data parameters. The system 0 also detects and corrects for DC offsets in the signal whose gain is controlled.
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83.发明公开Linear and non-linear dual mode transmitter 审中-公开Lineeer und Nichtlinearer Sender mit zwei Betriebsarten
公开(公告)号：EP1705800A2
公开(公告)日：2006-09-27
申请号：EP05026024.9
申请日：2005-11-29
Applicant: Broadcom Corporation
Inventor： Pan, Meng-An
CPC classification number: H04B1/0003 , H03F1/0261 , H03F3/45188 , H03G3/3042 , H03G2201/103 , H03G2201/202 , H03G2201/307 , H03G2201/40 , H04B1/0475
Abstract: A transmitter includes a dual mode modulator and an amplifier coupled to the dual mode modulator. The dual mode modulator implements a linear modulation scheme during a first mode of the modulator to produce a variable envelope modulated signal. The dual mode modulator implements a non-linear modulation scheme during a second mode of the modulator to produce a constant envelope modulated signal. The amplifier is biased as a linear amplifier during the first mode of the modulator and is biased as a non-linear amplifier during the second mode of the modulator. A feed-forward connection between the dual mode modulator and the amplifier is used to indicate a change in modulation mode and to adjust the bias of the amplifier. A power of the constant envelope modulated signal is increased such that an operating point of the amplifier remains substantially constant during the first and second modes of the modulator.
Abstract translation: 发射机包括耦合到双模调制器的双模调制器和放大器。 双模式调制器在调制器的第一模式期间实现线性调制方案，以产生可变包络调制信号。 双模调制器在调制器的第二模式期间实现非线性调制方案，以产生恒定的包络调制信号。 放大器在调制器的第一模式期间被偏置为线性放大器，并且在调制器的第二模式期间被偏置为非线性放大器。 双模式调制器和放大器之间的前馈连接用于指示调制模式的变化并调整放大器的偏置。 恒定包络调制信号的功率增加，使得放大器的工作点在调制器的第一和第二模式期间保持基本恒定。
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84.发明公开
公开(公告)号：EP1568192A1
公开(公告)日：2005-08-31
申请号：EP03783365.4
申请日：2003-11-14
Applicant: INTERDIGITAL TECHNOLOGY CORPORATION
Inventor： OZLUTURK, Fatih , KAZAKEVICH, Leonid , HAQUE, Tanbir , DEMIR, Alpaslan , NARAYAN, Geetha, Lakshmi , KEARNEY, Kenneth
IPC: H04M1/00
CPC classification number: H03G3/001 , H03D3/008 , H03D3/009 , H03G3/3068 , H03G3/3089 , H03G2201/103 , H03G2201/202 , H03G2201/302 , H03G2201/307 , H03G2201/508 , H04B1/30 , H04L2027/0016 , H04L2027/0024
Abstract: In order to compensate for performance degradation caused by inferior low-cost analog radio component (105) tolerances of an analog radio (100), a future system architecture (FSA) wireless communication transceiver employs numerous digital signal processing techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. Automatic gain control (110) functions are provided in the digital domain, so as to provide enhanced phase and amplitude compensation, as well as many other radio frequency parameters.
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公开(公告)号：JPWO2016113819A1
公开(公告)日：2017-10-19
申请号：JP2016569135
申请日：2015-12-22
Applicant: 株式会社ソシオネクスト
CPC classification number: H04B1/16 , H03F3/19 , H03F2200/294 , H03F2200/451 , H03G3/3036 , H03G3/3052 , H03G3/3078 , H03G2201/202 , H04B1/30
Abstract: 直流オフセットの発生を抑制するため、高周波信号をベースバンド信号に変換する検波器(50)を備えた無線受信機のための自動利得制御回路において、ベースバンド信号を可変の利得で増幅する増幅回路と当該増幅回路に結合された可変のカットオフ周波数を持つハイパスフィルタとを有する可変利得増幅器(60a,60b)と、利得制御信号を供給する制御部(80)と、高周波信号を一時的に遮断する遮断部(30)とを設ける。制御部(80)は、ハイパスフィルタのカットオフ周波数を高い値から低い値へ切り替える前に高周波信号の遮断を開始するように遮断部(30)を遮断制御信号で制御する。
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Patent Agency Ranking
公开(公告)号：JP4419545B2
公开(公告)日：2010-02-24
申请号：JP2003411131
申请日：2003-12-10
Applicant: 日本電気株式会社
Inventor： 賢二 寺尾
CPC classification number: H03G3/3078 , H03G3/3068 , H03G2201/103 , H03G2201/202 , H03G2201/302 , H03G2201/307
Abstract: In a slot format of a received signal, AGC gain update timings (t1 to t4) are shifted every time to disperse and reduce an influence of a noise attributable to a direct current component specific to direct conversion which is accompanied by AGC gain update. In particular, in the case where each of slots in the received signal includes an information portion (data) having a larger code correcting capability and an information portion having a smaller code correcting capability (TPC (transmission power control), TFCI (transport format combination indicator), PILOT), the AGC gain update timing is generated while being shifted in the former information portion, thereby reduce the influence of the noise. When the amount of shift of the AGC gain update timing is set to be larger than that of one symbol of the received signal, the influence of the noise accompanied by the AGC gain update is further reduced.
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公开(公告)号：JP2005286806A
公开(公告)日：2005-10-13
申请号：JP2004099582
申请日：2004-03-30
Inventor： ISHIHARA TAKESHI
IPC: H03G3/20 , H03F3/45 , H03G3/00 , H03G3/30 , H03M1/12 , H03M1/18 , H04B1/06 , H04B1/16 , H04B7/00
CPC classification number: H04W52/22 , H03G3/3068 , H03G2201/103 , H03G2201/202 , H03G2201/305 , H03G2201/307 , H03G2201/702 , H03M1/122 , H03M1/18 , H03M1/183
Abstract: PROBLEM TO BE SOLVED: To provide an automatic gain control device and the automatic gain control method which converge control action in a stable state during a short period of time in changing frequency of a receiving radio signal which occurs at the time of a compressed mode of WCDMA (Wideband Code Division Multiple Access), etc.
SOLUTION: A memory device storing a gain setting value is installed in the automatic gain control device, in changing frequency of the receiving signal from a gain setting value stored in the past, the device predicts and calculates the optimal gain setting value corresponding to a frequency after the change is carried out. The changing over of the frequency is carried out using the gain setting value which is predicted and calculated.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供一种自动增益控制装置和自动增益控制方法，其在短时间内将控制动作在稳定状态下收敛，以改变在接收无线电信号发生时的接收无线电信号的频率 WCDMA（宽带码分多址）的压缩模式等。解决方案：存储增益设定值的存储装置安装在自动增益控制装置中，从存储在存储器中的增益设定值改变接收信号的频率 过去，设备预测并计算与执行改变之后的频率对应的最佳增益设置值。 使用预测和计算的增益设定值来进行频率的切换。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：KR1020090043611A
公开(公告)日：2009-05-06
申请号：KR1020097007308
申请日：2003-11-14
Applicant: 인터디지탈 테크날러지 코포레이션
CPC classification number: H03G3/001 , H03D3/008 , H03D3/009 , H03G3/3068 , H03G3/3089 , H03G2201/103 , H03G2201/202 , H03G2201/302 , H03G2201/307 , H03G2201/508 , H04B1/30 , H04L2027/0016 , H04L2027/0024
Abstract: 아날로그 무선 기기(100)의 열등한 저비용 아날로그 무선 컴포넌트(105)에 의해 야기되는 성능 저하를 보상하기 위해서, 미래 시스템 아키텍처(FSA) 무선 시스템 트랜시버는 수많은 디지털 신호 처리 기술을 사용하여 현재 사양이 완화될 수 있도록 이러한 아날로그 컴포넌트의 결함을 보상한다. 자동 이득 제어(110)는 개선된 위상 및 진폭 보상만 아니라 많은 다른 무선 주파수 파라미터를 제공하도록 디지털 도메인에 제공된다.
무선 컴포넌트, 미래 시스템 아키텍처, 자동 이득 제어, 진폭 보상, 무선 송수신 유닛, RF 파라미터-
公开(公告)号：KR1020050086659A
公开(公告)日：2005-08-30
申请号：KR1020057008719
申请日：2003-11-14
Applicant: 인터디지탈 테크날러지 코포레이션
CPC classification number: H03G3/001 , H03D3/008 , H03D3/009 , H03G3/3068 , H03G3/3089 , H03G2201/103 , H03G2201/202 , H03G2201/302 , H03G2201/307 , H03G2201/508 , H04B1/30 , H04L2027/0016 , H04L2027/0024
Abstract: In order to compensate for performance degradation caused by inferior low-cost analog radio component (105) tolerances of an analog radio (100), a future system architecture (FSA) wireless communication transceiver employs numerous digital signal processing techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. Automatic gain control (110) functions are provided in the digital domain, so as to provide enhanced phase and amplitude compensation, as well as many other radio frequency parameters.
Abstract translation: 为了补偿由模拟无线电（100）的较差的低成本模拟无线电组件（105）容限引起的性能降低，未来系统架构（FSA）无线通信收发器采用大量数字信号处理技术来补偿这样的缺陷 模拟组件，以便现代规格可以放宽。 在数字域中提供了自动增益控制（110）功能，以便提供增强的相位和幅度补偿以及许多其他射频参数。
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公开(公告)号：JP4152983B2
公开(公告)日：2008-09-17
申请号：JP2005504575
申请日：2003-07-25
Applicant: 富士通株式会社
IPC: H04B17/40 , H04J3/00 , H03G3/00 , H03G3/20 , H03G3/30 , H04B1/16 , H04B1/707 , H04B7/005 , H04J11/00 , H04J13/00
CPC classification number: H03G3/3052 , H03G3/005 , H03G3/3078 , H03G3/3089 , H03G2201/103 , H03G2201/202 , H03G2201/305 , H04B1/707 , H04B2201/70701 , H04B2201/70706
Abstract: A received frame is branched into a gain control system (20A) for common pilot signals and a gain control system (20B) for individual data signals. The gain control system (20A) controls the gain of the common pilot signals, and the gain control system (20B) controls the gain of the data signals. A signal processor (30) establishes synchronization of frames, outputs a gain control signal (g1) so that the gain of the common pilot signal is constant, to a gain control circuit (21a) for the common pilot signals, and outputs a gain control signal (g2) so that the gain of the data signal is constant, to a gain control circuit (21b) for the data signals. The gain is controlled to be constant, thereby preventing saturation of ADC (26a, 26b, 27a, 27b) and S/N deterioration.
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