公开(公告)号：US09229466B2

公开(公告)日：2016-01-05

申请号：US13977460

申请日：2011-12-31

Applicant: Ruchir Saraswat ,  Andre Schaefer ,  Uwe Zillman ,  Andreas Duevel ,  Valluri Rao ,  Telesphor Kamgaing ,  Harish Krishnamurthy

Inventor： Ruchir Saraswat ,  Andre Schaefer ,  Uwe Zillman ,  Andreas Duevel ,  Valluri Rao ,  Telesphor Kamgaing ,  Harish Krishnamurthy

IPC: H01L27/06 ,  G05F1/618 ,  H02M3/156 ,  H01L25/065 ,  H01L27/02 ,  H01L49/02 ,  H01L23/48 ,  H01L23/64 ,  H01L25/18 ,  H01L23/522 ,  H02M7/00

CPC classification number: G05F1/618 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H02M3/156 ,  H02M7/003 ,  H01L2924/00

Abstract: A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically coupled to the inductor and is also located on the die, and a capacitor that is electrically coupled to the inductor and the voltage controller and is also located on the die. The inductor defines an interior space and the voltage controller and the capacitor are located within the interior space of the inductor. The inductor can be a lateral inductor or a through layer via inductor. The multi-stack integrated circuit may have multiple dies. A voltage controller may be electrically coupled to each of the dies, although it may be located on only one of the dies. Alternatively, separate voltage controllers may be electrically coupled to each of the multiple dies and may be located on each of the respective dies.

Abstract translation: 用于多堆叠集成电路中的一个或多个管芯的电压调节器包括位于管芯上的电感器，电耦合到电感器并且还位于管芯上的电压控制器，以及电耦合到 电感和电压控制器，也位于模具上。 电感器定义了内部空间，电压控制器和电容器位于电感器的内部空间内。 电感器可以是横向电感器或通过电感器的贯穿层。 多层集成电路可以具有多个管芯。 电压控制器可以电耦合到每个模具，尽管它可以仅位于一个模具上。 或者，单独的电压控制器可以电耦合到多个管芯中的每个，并且可以位于每个相应的管芯上。

公开(公告)号：US20130335059A1

公开(公告)日：2013-12-19

申请号：US13977460

申请日：2011-12-31

Applicant: Ruchir Saraswat ,  Andre Schaefer ,  Uwe Zillman ,  Andreas Duevel ,  Valluri Rao ,  Telesphor Kamgaing ,  Harish Krishnamurthy

Inventor： Ruchir Saraswat ,  Andre Schaefer ,  Uwe Zillman ,  Andreas Duevel ,  Valluri Rao ,  Telesphor Kamgaing ,  Harish Krishnamurthy

IPC: G05F1/618

CPC classification number: G05F1/618 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H02M3/156 ,  H02M7/003 ,  H01L2924/00

Abstract: A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically coupled to the inductor and is also located on the die, and a capacitor that is electrically coupled to the inductor and the voltage controller and is also located on the die. The inductor defines an interior space and the voltage controller and the capacitor are located within the interior space of the inductor. The inductor can be a lateral inductor or a through layer via inductor. The multi-stack integrated circuit may have multiple dies. A voltage controller may be electrically coupled to each of the dies, although it may be located on only one of the dies. Alternatively, separate voltage controllers may be electrically coupled to each of the multiple dies and may be located on each of the respective dies.

Abstract translation: 用于多堆叠集成电路中的一个或多个管芯的电压调节器包括位于管芯上的电感器，电耦合到电感器并且还位于管芯上的电压控制器，以及电耦合到 电感和电压控制器，也位于模具上。 电感器定义了内部空间，电压控制器和电容器位于电感器的内部空间内。 电感器可以是横向电感器或通过电感器的贯穿层。 多层集成电路可以具有多个管芯。 电压控制器可以电耦合到每个模具，尽管它可以仅位于一个模具上。 或者，单独的电压控制器可以电耦合到多个管芯中的每个，并且可以位于每个相应的管芯上。

公开(公告)号：US09673268B2

公开(公告)日：2017-06-06

申请号：US13976439

申请日：2011-12-29

Applicant: Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

Inventor： Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/52 ,  H01L29/92 ,  H01L49/02 ,  H01F7/06 ,  H01F5/00 ,  H01L23/522 ,  H01F17/00 ,  H01L27/06 ,  H01L27/08

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F2017/002 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/08 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

公开(公告)号：US20140027880A1

公开(公告)日：2014-01-30

申请号：US13976439

申请日：2011-12-29

Applicant: Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

Inventor： Andreas Duevel ,  Telesphor Kamgaing ,  Valluri R. Rao ,  Uwe Zillmann

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F2017/002 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/08 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

Abstract translation: 使用导电贯穿体通孔在集成电路管芯中形成三维电感器，该穿通体通孔穿过管芯的主体并与管芯前侧上的一个或多个金属互连层接触并终止在管芯的背面 死。 在另一个实施例中，通孔通孔可以穿过设置在管芯主体中的插塞中的电介质材料。 另一方面，变压器可以通过耦合使用通孔通孔形成的多个电感器来形成。 在另一方面，三维电感器可以包括由片上金属化层的堆叠形成的导体和设置在金属化层之间的绝缘层中的导电贯通层通孔。 描述其他实施例。