公开(公告)号：US20160306566A1

公开(公告)日：2016-10-20

申请号：US15038031

申请日：2013-12-26

Applicant: Shih-Lien L. Lu ,  Chun Shiah ,  Bordoou Rong ,  Andre Schaefer

Inventor： Shih-Lien L. Lu ,  Chun Shiah ,  Bordoou Rong ,  Andre Schaefer

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30101 ,  G06F12/0607 ,  G06F13/385

Abstract: Embodiments including systems, methods, and apparatuses associated with reordering data retrieved from a dynamic random access memory (DRAM). A memory controller may be configured to receive an instruction from a central processing unit (CPU) and, based on the instruction, retrieve a sequential data from a DRAM. The memory controller may then be configured to reorder the sequential data and place the reordered data in one or more locations of a vector register file.

Abstract translation: 包括与从动态随机存取存储器（DRAM）检索的重新排序数据相关联的系统，方法和装置的实施例。 存储器控制器可以被配置为从中央处理单元（CPU）接收指令，并且基于该指令从DRAM中检索顺序数据。 存储器控制器然后可以被配置为重新排序顺序数据并将重新排序的数据放置在向量寄存器文件的一个或多个位置中。

公开(公告)号：US20150380072A1

公开(公告)日：2015-12-31

申请号：US14320249

申请日：2014-06-30

Applicant: ANDRE SCHAEFER

Inventor： ANDRE SCHAEFER

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4076 ,  G11C11/4091 ,  G11C2211/4065 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: A refresh voltage control engine selectively applies different high voltages to use in refresh operations. The control engine can detect that a portion of a memory device needs to be refreshed, and determine that the refresh cycle time is too short for a state of the portion of the memory device. The memory device typically has an associated refresh cycle time or time between refreshes based on the device and system architecture. The control engine can generate one or more control signals to cause the system to apply an overcharge refresh to overcharge the portion of the memory device with a refresh operation to extend the refresh cycle time for the portion of the memory device.

Abstract translation: 刷新电压控制引擎选择性地施加不同的高电压以用于刷新操作。 控制引擎可以检测存储器件的一部分需要刷新，并且确定刷新周期时间对于存储器件的该部分的状态来说太短。 存储器件通常具有基于设备和系统架构的刷新之间的相关联的刷新周期时间或时间。 控制引擎可以产生一个或多个控制信号，以使系统施加过充电刷新，以使刷新操作对存储器件的一部分进行过充电，以延长存储器件部分的刷新周期时间。

公开(公告)号：US09074631B2

公开(公告)日：2015-07-07

申请号：US13994261

申请日：2011-08-22

Applicant: Christian Horn ,  Marc-Andre Schaefer

Inventor： Christian Horn ,  Marc-Andre Schaefer

IPC: F16C43/04 ,  F16C33/37 ,  F16C33/44 ,  F16C19/40 ,  F16C33/46 ,  F16C19/54

CPC classification number: F16C33/4605 ,  F16C19/364 ,  F16C19/54 ,  F16C19/548 ,  F16C41/04 ,  F16C2326/02

Abstract: A wheel bearing arrangement with first rolling elements, which are capable of rolling on a first inner ring, wherein the rolling elements are guided by a first roller bearing cage, and an axial spacer element is provided for spacing apart the first inner ring from a bearing element, wherein the bearing element can in particular be a second inner ring. The intention is to facilitate the complex installation of the individual parts in wheel bearings for utility vehicles. The first rolling element cage forms, together with the axial spacer element, an axial form-fitting connection. The spacer element can be fixed to at least one of the inner rings via the form-fitting connection to the cage prior to tightening the wheel hub, together with the wheel bearing preinstalled thereon.

Abstract translation: 一种具有第一滚动元件的车轮轴承装置，其能够在第一内圈上滚动，其中滚动元件由第一滚子轴承保持架引导，并且设置有轴向间隔元件用于将第一内圈与轴承 元件，其中所述轴承元件可以特别地是第二内圈。 其目的是为了便于将各个部件复杂地安装在用于多用途车辆的车轮轴承中。 第一滚动元件保持架与轴向隔离元件一起形成轴向形状连接。 与预先安装在其上的车轮轴承一起，在紧固轮毂之前，间隔元件可以经由与轿厢的形状配合连接而固定到至少一个内环。

公开(公告)号：US09000577B2

公开(公告)日：2015-04-07

申请号：US13976562

申请日：2011-09-30

Applicant: Guido Droege ,  Niklas Linkewitsch ,  Andre Schaefer

Inventor： Guido Droege ,  Niklas Linkewitsch ,  Andre Schaefer

IPC: H01L23/02 ,  H01L23/522 ,  H01L25/065 ,  H01L23/64 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Abstract translation: 一些实施例为3D堆叠模块提供电容AC耦合层间通信。

公开(公告)号：US20140325136A1

公开(公告)日：2014-10-30

申请号：US14327127

申请日：2014-07-09

Applicant: Andre Schaefer ,  John B. Halbert

Inventor： Andre Schaefer ,  John B. Halbert

IPC: G11C11/4074 ,  G06F1/32

CPC classification number: G11C11/4074 ,  G06F1/3275 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4045 ,  G11C11/4085 ,  Y02D10/14

Abstract: Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.

公开(公告)号：US20140183691A1

公开(公告)日：2014-07-03

申请号：US13730331

申请日：2012-12-28

Applicant: Ruchir Saraswat ,  Uwe Zillmann ,  Andre Schaefer ,  Tor Lund-Larsen

Inventor： Ruchir Saraswat ,  Uwe Zillmann ,  Andre Schaefer ,  Tor Lund-Larsen

IPC: H01L27/06

CPC classification number: H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2223/6616 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit.

Abstract translation: 谐振时钟三维堆叠器件。 装置的实施例包括：堆叠，其包括集成电路管芯; 并且通过至少一个管芯的硅通孔，其中穿过硅通孔的至少第一通孔硅通道包括电容结构或电感结构，所述第一穿硅通孔形成在所述多个管芯的第一管芯中 。 该装置包括谐振电路，第一通孔硅用作谐振电路的第一电路元件。

公开(公告)号：US20140006702A1

公开(公告)日：2014-01-02

申请号：US13538881

申请日：2012-06-29

Applicant: Tsun Ho Liu ,  Andre Schaefer ,  Hoi M. Ng ,  Guy R. Murray ,  Oleg Mikulchenko ,  Xiaofang Gao

Inventor： Tsun Ho Liu ,  Andre Schaefer ,  Hoi M. Ng ,  Guy R. Murray ,  Oleg Mikulchenko ,  Xiaofang Gao

IPC: G06F12/00

CPC classification number: G06F11/3037 ,  G06F1/3275 ,  G06F11/3058 ,  G06F11/3409 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4096 ,  Y02D10/13 ,  Y02D10/14

Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.

Abstract translation: 描述了根据本发明的一个实施例的用于促进对跟踪在存储器系统中的不同热条件下的数据眼动的写跟踪的机制。 本发明的实施例的方法包括监视与计算系统处的存储器系统的多个存储器件的存储器件相关联的有效数据眼睛的移动。 监视可以包括在与有效数据眼睛相关联的一个或多个刷新周期期间启动写入命令。 该方法可以包括确定数据眼的运动中的漂移，以及基于调整与数据眼的运动相关联的一个或多个现有的相位内插器值来校正漂移。

公开(公告)号：US20130335059A1

公开(公告)日：2013-12-19

申请号：US13977460

申请日：2011-12-31

Applicant: Ruchir Saraswat ,  Andre Schaefer ,  Uwe Zillman ,  Andreas Duevel ,  Valluri Rao ,  Telesphor Kamgaing ,  Harish Krishnamurthy

Inventor： Ruchir Saraswat ,  Andre Schaefer ,  Uwe Zillman ,  Andreas Duevel ,  Valluri Rao ,  Telesphor Kamgaing ,  Harish Krishnamurthy

IPC: G05F1/618

CPC classification number: G05F1/618 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L28/10 ,  H01L28/40 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H02M3/156 ,  H02M7/003 ,  H01L2924/00

Abstract: A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically coupled to the inductor and is also located on the die, and a capacitor that is electrically coupled to the inductor and the voltage controller and is also located on the die. The inductor defines an interior space and the voltage controller and the capacitor are located within the interior space of the inductor. The inductor can be a lateral inductor or a through layer via inductor. The multi-stack integrated circuit may have multiple dies. A voltage controller may be electrically coupled to each of the dies, although it may be located on only one of the dies. Alternatively, separate voltage controllers may be electrically coupled to each of the multiple dies and may be located on each of the respective dies.

Abstract translation: 用于多堆叠集成电路中的一个或多个管芯的电压调节器包括位于管芯上的电感器，电耦合到电感器并且还位于管芯上的电压控制器，以及电耦合到 电感和电压控制器，也位于模具上。 电感器定义了内部空间，电压控制器和电容器位于电感器的内部空间内。 电感器可以是横向电感器或通过电感器的贯穿层。 多层集成电路可以具有多个管芯。 电压控制器可以电耦合到每个模具，尽管它可以仅位于一个模具上。 或者，单独的电压控制器可以电耦合到多个管芯中的每个，并且可以位于每个相应的管芯上。

公开(公告)号：US20130272049A1

公开(公告)日：2013-10-17

申请号：US13997148

申请日：2011-12-02

Applicant: Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

Inventor： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

IPC: G11C5/06 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Abstract translation: 用于具有提供偏移互连的接口的堆叠存储器的操作的动态操作。 存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈，存储器堆栈包括一个或多个存储器管芯层。 每个存储器管芯层包括第一面和第二面，每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。 每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。

公开(公告)号：US08135936B2

公开(公告)日：2012-03-13

申请号：US12646248

申请日：2009-12-23

Applicant: Andre Schaefer ,  Matthias Gries

Inventor： Andre Schaefer ,  Matthias Gries

IPC: G06F12/06 ,  G06F12/10

CPC classification number: G06F12/10 ,  G06F12/0607 ,  Y02D10/13

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract translation: 系统监视并动态地改变计算系统运行时的内存映射。 计算系统具有各种存储器资源，以及多种可能的映射，其指示如何将数据存储在存储器资源中并随后从存储器资源访问。 在计算设备的不同运行时或负载条件下，每个存储器映射的性能可能不同。 内存控制器可以监视当前内存映射的运行时性能，并根据内存映射的监视或观察性能在运行时动态更改内存映射。 性能监视可以在系统中从字节级别到存储器通道的任意数量的不同粒度进行修改。