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    SELECTIVE REPLICATION OF DATA STRUCTURE
    4.
    发明申请
    SELECTIVE REPLICATION OF DATA STRUCTURE 审中-公开
    数据结构的选择性复制

    公开(公告)号：WO2006031551A2

    公开(公告)日：2006-03-23

    申请号：PCT/US2005031803

    申请日：2005-09-09

    Applicant: CAVIUM NETWORKS ,  BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E

    Inventor： BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E

    CPC classification number: G06F12/06 ,  G06F12/0653 ,  G06F2212/174

    Abstract: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data, structures that are loaded (i.e., read) more often than they are stored (i.e., written).

    Abstract translation: 提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。 存储器包括被配置为存储相同数据结构的复制副本的多个单独存储器组。 在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。 可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。 受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和其他数据，比它们被存储（即写入）更多的载体（即读）的结构。

    PACKET QUEUING, SCHEDULING AND ORDERING
    5.
    发明申请
    PACKET QUEUING, SCHEDULING AND ORDERING 审中-公开
    分组排队，排班和订购

    公开(公告)号：WO2006031459A1

    公开(公告)日：2006-03-23

    申请号：PCT/US2005/031219

    申请日：2005-09-01

    Applicant: CAVIUM NETWORKS ,  BOUCHARD, Gregg, A. ,  HUMMEL, Thomas, F. ,  KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R. ,  LEE, Yen

    Inventor： BOUCHARD, Gregg, A. ,  HUMMEL, Thomas, F. ,  KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R. ,  LEE, Yen

    IPC: G06F15/16 ,  H04L12/56

    CPC classification number: H04L12/56 ,  H04L47/50 ,  H04L63/164 ,  H04L63/166

    Abstract: A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the phase. A tag switch operation initiated by a core switches a tag dependent on the phase. A dedicated tag switch bus minimizes latency for the tag switch operation.

    Abstract translation: 提供了一种用于在多核网络服务处理器中排序，同步和调度工作的方法和装置。 每个工作都由一个标签标识，指示工作如何同步和排序。 通过在不同的处理器核心上并行处理具有不同标签的工作来增加吞吐量。 分组处理可以分解成不同的阶段，每个阶段具有取决于阶段的排序和同步约束的不同标签。 由核心发起的标签交换操作根据相位切换标签。 专用标签交换总线最大限度地减少了标签交换操作的延迟。

    DIRECT ACCESS TO LOW-LATENCY MEMORY
    7.
    发明申请
    DIRECT ACCESS TO LOW-LATENCY MEMORY 审中-公开
    直接访问低延迟存储器

    公开(公告)号：WO2006031462A9

    公开(公告)日：2006-08-24

    申请号：PCT/US2005031295

    申请日：2005-09-01

    Applicant: CAVIUM NETWORKS ,  BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    Inventor： BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    IPC: G06F9/312 ,  G06F12/08

    CPC classification number: G06F9/3824 ,  G06F9/3885 ,  G06F12/0888

    Abstract: A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

    Abstract translation: 提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。 该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。 系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。 非普通的加载/存储指令可以是协处理器指令。 存储器可以是低延迟型存储器。 处理器可以包括多个处理器核。

    SELECTIVE REPLICATION OF DATA STRUCTURE
    8.
    发明申请
    SELECTIVE REPLICATION OF DATA STRUCTURE 审中-公开

    公开(公告)号：WO2006031551A3

    公开(公告)日：2006-03-23

    申请号：PCT/US2005/031803

    申请日：2005-09-09

    Applicant: CAVIUM NETWORKS ,  BOUCHARD, Gregg, A. ,  CARLSON, David, A. ,  KESSLER, Richard, E.

    Inventor： BOUCHARD, Gregg, A. ,  CARLSON, David, A. ,  KESSLER, Richard, E.

    IPC: G06F12/06 ,  G06F13/16

    Abstract: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data, structures that are loaded (i.e., read) more often than they are stored (i.e., written).

    IPSEC PERFORMANCE OPTIMIZATION
    9.
    发明申请
    IPSEC PERFORMANCE OPTIMIZATION 审中-公开
    IPSEC性能优化

    公开(公告)号：WO2004093373A3

    公开(公告)日：2005-04-14

    申请号：PCT/US2004009835

    申请日：2004-03-31

    Applicant: CAVIUM NETWORKS ,  BOUCHARD GREGG A ,  KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    Inventor： BOUCHARD GREGG A ,  KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    IPC: H04L29/06 ,  H04L9/00 ,  G06F15/16 ,  H04L9/32

    CPC classification number: H04L63/0485 ,  H04L63/1466 ,  H04L63/164

    Abstract: A method and apparatus for optimizing IPsec processing by providing execution units with windowing data during prefetch and managing coherency of security association data by management of security association accesses. Providing execution units with windowing data allows initial parallel processing of IPsec packets. The security association access ordering apparatus serializes access to the dynamic section of security association data according to packet order arrival while otherwise allowing parallel processing of the IPsec packet by multiple execution units in a security processor.

    Abstract translation: 一种通过在预取期间向执行单元提供窗口数据并通过管理安全关联访问来管理安全关联数据的一致性来优化IPsec处理的方法和装置。 为执行单元提供窗口数据允许IPsec数据包的初始并行处理。 安全关联访问排序装置根据分组顺序序列化对安全关联数据的动态部分的访问，而另外允许在安全处理器中由多个执行单元并行处理IPsec分组。

    IPSEC PERFORMANCE OPTIMIZATION
    10.
    发明申请
    IPSEC PERFORMANCE OPTIMIZATION 审中-公开
    IPSEC性能优化

    公开(公告)号：WO2004093373A2

    公开(公告)日：2004-10-28

    申请号：PCT/US2004/009835

    申请日：2004-03-31

    Applicant: CAVIUM NETWORKS ,  BOUCHARD, Gregg, A. ,  KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R.

    Inventor： BOUCHARD, Gregg, A. ,  KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R.

    IPC: H04L

    CPC classification number: H04L63/0485 ,  H04L63/1466 ,  H04L63/164

    Abstract: A method and apparatus for optimizing IPsec processing by providing execution units with windowing data during prefetch and managing coherency of security association data by management of security association accesses. Providing execution units with windowing data allows initial parallel processing of IPsec packets. The security association access ordering apparatus serializes access to the dynamic section of security association data according to packet order arrival while otherwise allowing parallel processing of the IPsec packet by multiple execution units in a security processor.

    Abstract translation: 一种通过在预取期间向执行单元提供窗口数据并通过管理安全关联访问来管理安全关联数据的一致性来优化IPsec处理的方法和装置。 为执行单元提供窗口数据允许IPsec数据包的初始并行处理。 安全关联访问排序装置根据分组顺序序列化对安全关联数据的动态部分的访问，而另外允许在安全处理器中由多个执行单元并行处理IPsec分组。

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