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    PACKET QUEUING, SCHEDULING AND ORDERING
    1.
    发明申请
    PACKET QUEUING, SCHEDULING AND ORDERING 审中-公开
    分组排队，排班和订购

    公开(公告)号：WO2006031459A1

    公开(公告)日：2006-03-23

    申请号：PCT/US2005/031219

    申请日：2005-09-01

    Applicant: CAVIUM NETWORKS ,  BOUCHARD, Gregg, A. ,  HUMMEL, Thomas, F. ,  KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R. ,  LEE, Yen

    Inventor： BOUCHARD, Gregg, A. ,  HUMMEL, Thomas, F. ,  KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R. ,  LEE, Yen

    IPC: G06F15/16 ,  H04L12/56

    CPC classification number: H04L12/56 ,  H04L47/50 ,  H04L63/164 ,  H04L63/166

    Abstract: A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the phase. A tag switch operation initiated by a core switches a tag dependent on the phase. A dedicated tag switch bus minimizes latency for the tag switch operation.

    Abstract translation: 提供了一种用于在多核网络服务处理器中排序，同步和调度工作的方法和装置。 每个工作都由一个标签标识，指示工作如何同步和排序。 通过在不同的处理器核心上并行处理具有不同标签的工作来增加吞吐量。 分组处理可以分解成不同的阶段，每个阶段具有取决于阶段的排序和同步约束的不同标签。 由核心发起的标签交换操作根据相位切换标签。 专用标签交换总线最大限度地减少了标签交换操作的延迟。

    TRANSPARENT IPSEC PROCESSING INLINE BETWEEN A FRAMER AND A NETWORK COMPONENT
    2.
    发明申请
    TRANSPARENT IPSEC PROCESSING INLINE BETWEEN A FRAMER AND A NETWORK COMPONENT 审中-公开
    框架和网络组件之间的透明IPSEC处理

    公开(公告)号：WO2004092930A3

    公开(公告)日：2005-05-26

    申请号：PCT/US2004009738

    申请日：2004-03-30

    Applicant: CAVIUM NETWORKS ,  KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    Inventor： KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    IPC: H04L29/06 ,  H04L9/00 ,  G06F15/16

    CPC classification number: H04L63/045 ,  H04L63/0485 ,  H04L63/164

    Abstract: A method and apparatus for transparent processing of IPsec network traffic by a security processor (103) in line between a framer (101) and a network processor (105). Security processor (103) parses packet header and tail information to determine if encryption or decryption is required. After encryption or decryption is completed, packet header and tail information is modified to reflect the changes in the packet such as length of the packet. The modified packet is then passed on to the network processor (105) or framer (101).

    Abstract translation: 一种用于通过成帧器（101）和网络处理器（105）之间的线路的安全处理器（103）透明地处理IPsec网络流量的方法和装置。 安全处理器（103）解析分组报头和尾部信息以确定是否需要加密或解密。 在完成加密或解密之后，修改分组报头和尾部信息以反映分组中的变化，例如分组的长度。 然后将经修改的分组传递到网络处理器（105）或成帧器（101）。

    DIRECT ACCESS TO LOW-LATENCY MEMORY
    3.
    发明申请
    DIRECT ACCESS TO LOW-LATENCY MEMORY 审中-公开
    直接访问低延迟存储器

    公开(公告)号：WO2006031462A9

    公开(公告)日：2006-08-24

    申请号：PCT/US2005031295

    申请日：2005-09-01

    Applicant: CAVIUM NETWORKS ,  BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    Inventor： BOUCHARD GREGG A ,  CARLSON DAVID A ,  KESSLER RICHARD E ,  HUSSAIN MUHAMMAD R

    IPC: G06F9/312 ,  G06F12/08

    CPC classification number: G06F9/3824 ,  G06F9/3885 ,  G06F12/0888

    Abstract: A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

    Abstract translation: 提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。 该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。 系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。 非普通的加载/存储指令可以是协处理器指令。 存储器可以是低延迟型存储器。 处理器可以包括多个处理器核。

    TRANSPARENT IPSEC PROCESSING INLINE BETWEEN A FRAMER AND A NETWORK COMPONENT
    4.
    发明申请
    TRANSPARENT IPSEC PROCESSING INLINE BETWEEN A FRAMER AND A NETWORK COMPONENT 审中-公开
    框架和网络组件之间的透明IPSEC处理

    公开(公告)号：WO2004092930A2

    公开(公告)日：2004-10-28

    申请号：PCT/US2004/009738

    申请日：2004-03-30

    Applicant: CAVIUM NETWORKS ,  KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R.

    Inventor： KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R.

    IPC: G06F

    CPC classification number: H04L63/045 ,  H04L63/0485 ,  H04L63/164

    Abstract: A method and apparatus for transparent processing of IPsec network traffic by a security processor in line between a framer and a network processor. Security processor parses packet header and tail information to determine if encryption or decryption is required. After encryption or decryption is completed packet header and tail information is modified to reflect the changes in the packet such as length of the packet. The modified packet is then passed on to the network processor or framer.

    Abstract translation: 一种用于通过成帧器和网络处理器之间的安全处理器来透明处理IPsec网络流量的方法和装置。 安全处理器解析分组报头和尾部信息，以确定是否需要加密或解密。 在完成加密或解密之后，数据包头和尾信息被修改以反映分组中的变化，例如分组的长度。 修改后的数据包然后传递到网络处理器或成帧器。

    METHOD AND APPARATUS FOR POWER CONTROL
    5.
    发明申请
    METHOD AND APPARATUS FOR POWER CONTROL 审中-公开
    用于功率控制的方法和装置

    公开(公告)号：WO2011094148A1

    公开(公告)日：2011-08-04

    申请号：PCT/US2011/022217

    申请日：2011-01-24

    Applicant: CAVIUM, INC. ,  CARLSON, David, A. ,  KESSLER, Richard, E. ,  HAIDER, Amer

    Inventor： CARLSON, David, A. ,  KESSLER, Richard, E. ,  HAIDER, Amer

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/329 ,  G06F11/3058 ,  Y02D10/24 ,  Y10S323/907

    Abstract: Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the application.

    Abstract translation: 本发明的实施例涉及限制在处理器中发生的最大功率耗散。 因此，当正在执行需要过多功率的应用时，可以防止应用的执行以减少耗散或消耗的功率。 示例性实施例可以阻止处理器发出或执行指令，允许软件或硬件通过施加应用的性能的降低而降低应用的功率。

    DIRECT ACCESS TO LOW-LATENCY MEMORY
    8.
    发明申请
    DIRECT ACCESS TO LOW-LATENCY MEMORY 审中-公开
    直接访问低延迟内存

    公开(公告)号：WO2006031462A1

    公开(公告)日：2006-03-23

    申请号：PCT/US2005/031295

    申请日：2005-09-01

    Applicant: CAVIUM NETWORKS ,  BOUCHARD, Gregg, A. ,  CARLSON, David, A. ,  KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R.

    Inventor： BOUCHARD, Gregg, A. ,  CARLSON, David, A. ,  KESSLER, Richard, E. ,  HUSSAIN, Muhammad, R.

    IPC: G06F9/312 ,  G06F12/08

    CPC classification number: G06F9/3824 ,  G06F9/3885 ,  G06F12/0888

    Abstract: A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

    Abstract translation: 提供了一种内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致性存储器。 处理器包括用于缓存一致性存储器的系统接口和到非缓存一致性存储器的低延迟存储器接口。 系统接口将处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致性存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓冲存储器，由此绕过高速缓冲存储器相干存储器。 非普通加载/存储指令可以是协处理器指令。 内存可以是低延迟类型的内存。 处理器可以包括多个处理器核心。

    SELECTIVE REPLICATION OF DATA STRUCTURE
    10.
    发明申请
    SELECTIVE REPLICATION OF DATA STRUCTURE 审中-公开

    公开(公告)号：WO2006031551A3

    公开(公告)日：2006-03-23

    申请号：PCT/US2005/031803

    申请日：2005-09-09

    Applicant: CAVIUM NETWORKS ,  BOUCHARD, Gregg, A. ,  CARLSON, David, A. ,  KESSLER, Richard, E.

    Inventor： BOUCHARD, Gregg, A. ,  CARLSON, David, A. ,  KESSLER, Richard, E.

    IPC: G06F12/06 ,  G06F13/16

    Abstract: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data, structures that are loaded (i.e., read) more often than they are stored (i.e., written).

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