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    STACKED CHANNEL STRUCTURES FOR MOSFETS
    2.
    发明申请
    STACKED CHANNEL STRUCTURES FOR MOSFETS 审中-公开
    用于MOSFET的堆叠沟道结构

    公开(公告)号：WO2017095409A1

    公开(公告)日：2017-06-08

    申请号：PCT/US2015/063613

    申请日：2015-12-03

    Applicant: INTEL CORPORATION ,  MEHANDRU, Rishabh ,  KOTLYAR, Roza ,  CEA, Stephen, M. ,  KEYS, Patrick, H.

    Inventor： MEHANDRU, Rishabh ,  KOTLYAR, Roza ,  CEA, Stephen, M. ,  KEYS, Patrick, H.

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/78 ,  H01L21/8221 ,  H01L21/823807 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/1054

    Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.

    Abstract translation: 这里公开了用于金属氧化物半导体场效应晶体管（MOSFET）和相关电路元件，计算设备和方法的堆叠沟道结构。 例如，堆叠沟道结构可以包括：具有衬底晶格常数的半导体衬底; 延伸离开所述半导体衬底的鳍片，所述鳍片具有上部区域和下部区域; 在所述下部区域中的第一晶体管，其中所述第一晶体管具有第一沟道，所述第一沟道具有第一晶格常数，并且所述第一晶格常数不同于所述衬底晶格常数; 以及在上部区域中的第二晶体管，其中第二晶体管具有第二沟道，第二沟道具有第二晶格常数，并且第二晶格常数不同于衬底晶格常数。

    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED TRANSISTORS
    4.
    发明申请
    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED TRANSISTORS 审中-公开
    用于基于晶体的晶体管的高移动性应变通道

    公开(公告)号：WO2014018181A1

    公开(公告)日：2014-01-30

    申请号：PCT/US2013/045440

    申请日：2013-06-12

    Applicant: INTEL CORPORATION ,  CEA, Stephen M. ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  AUBERTINE, Daniel B. ,  GHANI, Tahir ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza

    Inventor： CEA, Stephen M. ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  AUBERTINE, Daniel B. ,  GHANI, Tahir ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric / semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric / semiconductor interface.

    Abstract translation: 公开了用于将高迁移率应变通道结合到鳍状晶体管（例如，诸如双栅极，三相等等的FinFET）中的技术，其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中，硅锗（SiGe）被包覆到硅散热片上以提供期望的应力，尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容，并且包层沉积可以发生在工艺流程内的多个位置处。 在一些情况下，来自包覆层的内置应力可以通过压缩通道中的鳍和覆层的源极/漏极应力来增强。 在一些情况下，可以提供可选的封盖层以改善栅极电介质/半导体界面。 在一个这样的实施例中，硅被提供在SiGe包覆层上以改善栅极电介质/半导体界面。

    BACKSIDE FIN RECESS CONTROL WITH MULTI-HSI OPTION
    9.
    发明申请
    BACKSIDE FIN RECESS CONTROL WITH MULTI-HSI OPTION 审中-公开
    具有多个HSI选项的背面熔接控制

    公开(公告)号：WO2017052604A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2015/052288

    申请日：2015-09-25

    Applicant: INTEL CORPORATION ,  LILAK, Aaron D. ,  MORROW, Patrick ,  CEA, Stephen M. ,  MEHANDRU, Rishabh ,  WEBER, Cory E.

    Inventor： LILAK, Aaron D. ,  MORROW, Patrick ,  CEA, Stephen M. ,  MEHANDRU, Rishabh ,  WEBER, Cory E.

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/78 ,  H01L21/26506 ,  H01L29/785

    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

    Abstract translation: 本发明的实施例涉及在三栅极或Fin-FET器件中形成具有不同有源沟道高度的翅片。 在一个实施例中，至少两个翅片形成在基板的正面上。 栅极结构在鳍的至少一部分的顶表面和一对侧壁上延伸。 在一个实施例中，将基板变薄以暴露翅片的底表面。 接下来，可以在每个鳍上执行背面蚀刻以形成有源沟道区。 翅片可以凹入到不同的深度，形成具有不同高度的有源通道区域。

    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS
    10.
    发明申请
    HIGH MOBILITY STRAINED CHANNELS FOR FIN-BASED NMOS TRANSISTORS 审中-公开
    用于基于FIN的NMOS晶体管的高移动性应变通道

    公开(公告)号：WO2015147836A1

    公开(公告)日：2015-10-01

    申请号：PCT/US2014/032039

    申请日：2014-03-27

    Applicant: INTEL CORPORATION ,  CEA, Stephen, M. ,  KOTLYAR, Roza ,  KENNEL, Harold, W. ,  GLASS, Glenn, A. ,  MURTHY, Anand, S. ,  RACHMADY, Willy ,  GHANI, Tahir

    Inventor： CEA, Stephen, M. ,  KOTLYAR, Roza ,  KENNEL, Harold, W. ,  GLASS, Glenn, A. ,  MURTHY, Anand, S. ,  RACHMADY, Willy ,  GHANI, Tahir

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/785 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818

    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, frigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow, in various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

    Abstract translation: 公开了用于将高迁移率应变通道结合到鳍状NMOS晶体管（例如，诸如双栅极，护卫舰等的FinFET）中的技术，其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中，锗或硅锗膜被包覆在硅散热片上，以便在散热片的芯中提供期望的拉伸应变，尽管可以使用其它的翅片和包层材料。 这些技术与典型的工艺流程兼容，并且在典型工艺流程中的多个位置处可以发生包层沉积，在各种实施例中，可以以最小宽度（或稍后变薄）形成翅片，以便提高晶体管性能。 在一些实施例中，变薄的翅片也增加穿过包覆翅片的芯的拉伸应变。 在一些情况下，通过添加嵌入式硅外延源和漏极可以进一步增强芯中的应变。

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