公开(公告)号：SG11201601319QA

公开(公告)日：2016-03-30

申请号：SG11201601319Q

申请日：2013-09-27

Applicant: INTEL CORP ,  PILLARISETTY RAVI ,  DASGUPTA SANSAPTAK ,  GOEL NITI ,  LE VAN H ,  RADOSAVLJEVIC MARKO ,  DEWEY GILBERT ,  MUKHERJEE NILOY ,  METZ MATTHEW V ,  RACHMADY WILLY ,  KAVALIEROS JACK T ,  CHU-KUNG BENJAMIN ,  KENNEL HAROLD W ,  CEA STEPHEN M ,  CHAU ROBERT S

Inventor： PILLARISETTY RAVI ,  DASGUPTA SANSAPTAK ,  GOEL NITI ,  LE VAN H ,  RADOSAVLJEVIC MARKO ,  DEWEY GILBERT ,  MUKHERJEE NILOY ,  METZ MATTHEW V ,  RACHMADY WILLY ,  KAVALIEROS JACK T ,  CHU-KUNG BENJAMIN ,  KENNEL HAROLD W ,  CEA STEPHEN M ,  CHAU ROBERT S

IPC: H01L21/336 ,  H01L29/78

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

公开(公告)号：WO2019066880A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054193

申请日：2017-09-28

Applicant: INTEL CORPORATION ,  MA, Sean T. ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  KENNEL, Harold W. ,  HUANG, Cheng-Ying ,  METZ, Matthew V. ,  MINUTILLO, Nicholas G. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S.

Inventor： MA, Sean T. ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  KENNEL, Harold W. ,  HUANG, Cheng-Ying ,  METZ, Matthew V. ,  MINUTILLO, Nicholas G. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S.

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: Group III-V semiconductor devices having asymmetric source and drain structures and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. The drain structure has a wider band gap than the source structure. A gate structure is over the channel structure.

公开(公告)号：WO2018236359A1

公开(公告)日：2018-12-27

申请号：PCT/US2017/038385

申请日：2017-06-20

Applicant: INTEL CORPORATION ,  DEWEY, Gilbert ,  LE, Van H. ,  SHARMA, Abhishek A. ,  SHIVARAMAN, Shriram ,  PILLARISETTY, Ravi ,  GHANI, Tahir ,  KAVALIEROS, Jack T.

Inventor： DEWEY, Gilbert ,  LE, Van H. ,  SHARMA, Abhishek A. ,  SHIVARAMAN, Shriram ,  PILLARISETTY, Ravi ,  GHANI, Tahir ,  KAVALIEROS, Jack T.

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: Thin film core-shell fin and nanowire transistors are described. In an example, an integrated circuit structure includes a fin on an insulator layer above a substrate. The fin has a top and sidewalls. The fin is composed of a first semiconducting oxide material. A second semiconducting oxide material is on the top and sidewalls of the fin. A gate electrode is over a first portion of the second semiconducting oxide material on the top and sidewalls of the fin. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact over a second portion of the second semiconducting oxide material on the top and sidewalls of the fin. A second conductive contact is adjacent the second side of the gate electrode, the second conductive contact over a third portion of the second semiconducting oxide material on the top and sidewalls of the fin.

公开(公告)号：WO2016043775A1

公开(公告)日：2016-03-24

申请号：PCT/US2014/056564

申请日：2014-09-19

Applicant: INTEL CORPORATION ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  GLASS, Glenn S. ,  GHANI, Tahir ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  METZ, Matthew V. ,  KAVALIEROS, Jack T.

Inventor： MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  GLASS, Glenn S. ,  GHANI, Tahir ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  METZ, Matthew V. ,  KAVALIEROS, Jack T.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66469 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851

Abstract: Transistor devices having a doped buffer or sub-structure between an active channel and a substrate. In one embodiment, a p-type dopant, such as magnesium, zinc, carbon, beryllium, and the like, may be introduced in the formation of the sub-structure, wherein the dopant may act as a p/n junction at the active channel to source and drain interfaces and decrease the off-state leakage path. In another embodiment, the material used for the formation of the doped substructure may be substantially the same as the material, without the dopant, used for the formation of the active channel, such that no heterojunction will be formed which could result in crystalline imperfections.

Abstract translation: 具有在有源沟道和衬底之间的掺杂缓冲层或子结构的晶体管器件。 在一个实施例中，可以在形成子结构中引入p型掺杂剂，例如镁，锌，碳，铍等，其中掺杂剂可以在有源沟道处作为ap / n结 到源极和漏极接口，并减少断开状态的泄漏路径。 在另一个实施方案中，用于形成掺杂子结构的材料可以与用于形成有源沟道的材料基本上不相同，因此不会形成可能导致晶体缺陷的异质结。

公开(公告)号：WO2013101001A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067661

申请日：2011-12-28

Applicant: INTEL CORPORATION ,  MUKHERJEE, Niloy ,  METZ, Matthew V. ,  POWERS, James M. ,  LE, Van H. ,  CHU-KING, Benjamin ,  LEMAY, Mark R. ,  RADOSAVLJEVIC, Marko ,  GOEL, Niti ,  CHOW, Loren ,  TOLCHINSKY, Peter G. ,  KAVALIEROS, Jack T. ,  CHAU, Robert S.

Inventor： MUKHERJEE, Niloy ,  METZ, Matthew V. ,  POWERS, James M. ,  LE, Van H. ,  CHU-KING, Benjamin ,  LEMAY, Mark R. ,  RADOSAVLJEVIC, Marko ,  GOEL, Niti ,  CHOW, Loren ,  TOLCHINSKY, Peter G. ,  KAVALIEROS, Jack T. ,  CHAU, Robert S.

IPC: H01L21/20 ,  H01L29/778

CPC classification number: H01L29/06 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/0259 ,  H01L21/02617 ,  H01L21/02636 ,  H01L21/02658 ,  H01L21/02664

Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

Abstract translation: 描述了在非天然表面上形成具有降低的表面粗糙度和体缺陷密度的异质层以及由此形成的器件的方法。 在一个实施例中，该方法包括提供具有晶格常数的顶表面并在衬底的顶表面上沉积第一层的衬底。 第一层具有不同于衬底顶表面的第一晶格常数的晶格常数的顶表面。 第一层被退火和抛光以形成抛光表面。 然后在抛光表面上方沉积第二层。

公开(公告)号：WO2013085534A1

公开(公告)日：2013-06-13

申请号：PCT/US2011/064096

申请日：2011-12-09

Applicant: INTEL CORPORATION ,  LE, Van H. ,  CHU-KUNG, Benjamin ,  KENNEL, Harold Hal W. ,  RACHMADY, Willy ,  PILLARISETTY, Ravi ,  KAVALIEROS, Jack T.

Inventor： LE, Van H. ,  CHU-KUNG, Benjamin ,  KENNEL, Harold Hal W. ,  RACHMADY, Willy ,  PILLARISETTY, Ravi ,  KAVALIEROS, Jack T.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

Abstract translation: 提供具有包括压缩和拉伸应变外延材料的交替层的沟道区的晶体管结构。 交替的外延层可以在单和多晶体管结构中形成沟道区。 在替代实施例中，两个交替层中的一个被选择性地蚀刻掉以形成剩余材料的纳米带或纳米线。 得到的应变纳米带或纳米线形成晶体管结构的沟道区。 还提供了包括晶体管的计算设备，所述晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区，以及包括包含由应变纳米带或纳米线组成的沟道区的晶体管的计算器件。

公开(公告)号：WO2012087581A2

公开(公告)日：2012-06-28

申请号：PCT/US2011/063813

申请日：2011-12-07

Applicant: INTEL CORPORATION ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  GHANI, Tahir ,  PILLARISETTY, Ravi ,  MUKHERJEE, Niloy ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza ,  RACHMADY, Willy ,  LIU, Mark Y.

Inventor： MURTHY, Anand S. ,  GLASS, Glenn A. ,  GHANI, Tahir ,  PILLARISETTY, Ravi ,  MUKHERJEE, Niloy ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza ,  RACHMADY, Willy ,  LIU, Mark Y.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm -3 . A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Abstract translation: 公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。 在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。 在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。 可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。 锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。 这些技术可以例如在平面或非平面晶体管器件中实现。

公开(公告)号：WO2012040075A3

公开(公告)日：2012-06-07

申请号：PCT/US2011052084

申请日：2011-09-19

Applicant: INTEL CORP ,  CEA STEPHEN M ,  KOTLYAR ROZA ,  KAVALIEROS JACK T ,  GILES MARTIN D ,  GHANI TAHIR ,  KUHN KELIN J ,  KUHN MARKUS ,  ZELICK NANCY M

Inventor： CEA STEPHEN M ,  KOTLYAR ROZA ,  KAVALIEROS JACK T ,  GILES MARTIN D ,  GHANI TAHIR ,  KUHN KELIN J ,  KUHN MARKUS ,  ZELICK NANCY M

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

Abstract translation: 根据该方法制造的方法和装置。 该方法包括提供包括第一材料的基底，并且提供包括第二材料的翅片，所述翅片设置在所述基底上并且具有器件活性部分，所述第一材料和所述第二材料在其各自的结晶结构之间呈现晶格失配 。 提供散热片包括在基板上提供包括第二材料的双轴应变膜; 并除去双轴应变膜的部分以形成基本上单轴应变的翅片。

公开(公告)号：WO2011087610A3

公开(公告)日：2011-10-20

申请号：PCT/US2010058784

申请日：2010-12-02

Applicant: INTEL CORP ,  KAVALIEROS JACK T ,  RACHMADY WILLY ,  MUKHERJEE NILOY ,  RADOSAVLJEVIC MARKO ,  GOE NITI ,  LEE YONG JU ,  MAJHI PRASHANT ,  TSAI WILMAN ,  DEWEY GILBERT

Inventor： KAVALIEROS JACK T ,  RACHMADY WILLY ,  MUKHERJEE NILOY ,  RADOSAVLJEVIC MARKO ,  GOE NITI ,  LEE YONG JU ,  MAJHI PRASHANT ,  TSAI WILMAN ,  DEWEY GILBERT

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Abstract translation: 描述了III-V半导体器件的导电性改进。 第一种改进包括与沟道层不共面的平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源极/漏极。 第三种改进包括在III-V沟道层上形成IV族和/或VI族元素层，并退火以III-V族沟道层掺杂IV族和/或VI族物质。 第四种改进包括形成在III-V器件的接入区域上方的钝化层和/或偶极子层。

公开(公告)号：WO2011087606A2

公开(公告)日：2011-07-21

申请号：PCT/US2010/058683

申请日：2010-12-02

Applicant: INTEL CORPORATION ,  PILLARISETTY, Ravi ,  KAVALIEROS, Jack, T. ,  CHU-KUNG, Benjamin ,  RACHMADY, Willy ,  HUDAIT, Mantu, K. ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert, S.

Inventor： PILLARISETTY, Ravi ,  KAVALIEROS, Jack, T. ,  CHU-KUNG, Benjamin ,  RACHMADY, Willy ,  HUDAIT, Mantu, K. ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  CHAU, Robert, S.

CPC classification number: H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Abstract translation: 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。