公开(公告)号：WO2009146344A1

公开(公告)日：2009-12-03

申请号：PCT/US2009/045372

申请日：2009-05-28

Applicant: MOTOROLA, INC. ,  GABATO, Manuel, P. Jr. ,  BOZEKI, John, J. ,  CHARASKA, Joseph, A. ,  GAILUS, Paul, H.

Inventor： GABATO, Manuel, P. Jr. ,  BOZEKI, John, J. ,  CHARASKA, Joseph, A. ,  GAILUS, Paul, H.

IPC: H03L7/089 ,  H03L7/197

CPC classification number: H03L7/1974 ,  H03L7/0893

Abstract: A method and apparatus for reducing in-band spurs in a fractional-N synthesizer (100) includes generating a compensated current signal by a charge pump (108) coupled to a phase detector (106). The compensated current signal includes in-band spurs having frequencies within a frequency bandwidth associated with a loop filter (110). The method then includes selectively dithering the compensated current signal with a sufficient dither level to spread the frequencies of in-band spurs beyond the frequency bandwidth associated with the loop filter (110). The dithered compensated current signal is then passed through the loop filter (110) for filtering the in-band spurs having frequencies beyond the frequency bandwidth. The method then includes generating a voltage controlled oscillator (VCO) signal with reduced in-band spurs proportional to the filtered compensated current signal.

Abstract translation: 用于减小分数N合成器（100）中的带内杂散的方法和装置包括通过耦合到相位检测器（106）的电荷泵（108）产生补偿的电流信号。 经补偿的电流信号包括具有与环路滤波器（110）相关联的频率带宽内的频率的带内杂散。 该方法然后包括以足够的抖动电平选择性地使经补偿的电流信号抖动，以将带内杂散的频率扩展到与环路滤波器（110）相关联的频率带宽之外。 抖动补偿电流信号然后通过环路滤波器（110），用于对频率超过频率带宽的带内杂散进行滤波。 该方法然后包括产生与经滤波的补偿电流信号成比例的减小的带内杂散的压控振荡器（VCO）信号。

公开(公告)号：WO2009042384A1

公开(公告)日：2009-04-02

申请号：PCT/US2008/075698

申请日：2008-09-09

Applicant: MOTOROLA, INC. ,  GAILUS, Paul, H. ,  BOZEKI, John, J. ,  CHARASKA, Joseph, A. ,  DUBOV, Vadim ,  GABATO, Manuel, P., Jr. ,  GONZALEZ, Armando, J.

Inventor： GAILUS, Paul, H. ,  BOZEKI, John, J. ,  CHARASKA, Joseph, A. ,  DUBOV, Vadim ,  GABATO, Manuel, P., Jr. ,  GONZALEZ, Armando, J.

IPC: H03L7/197

CPC classification number: H03L7/1974

Abstract: A frequency synthesizer (100) includes: a frequency source generating a reference signal (107) that includes a plurality of pulses having periodicity based on a reference frequency; a feedback loop that includes, a phase detector circuit (119), a loop filter (120), a controlled oscillator (121) that generates an output signal at an output (112), and a loop divide circuit (122); a non-linear circuit element (103) at an input of the phase detector circuit (119), which generates intermodulation distortion that causes at least one spurious signal at the output; and a controller (106) controlling the loop divide circuit (122) and the non-linear circuit element (103). The frequency synthesizer further includes a dither circuit (101) that adjusts the timing of some of the pulses of the reference signal based on a parameter provided by the controller (106) to the non-linear circuit element (103), thereby, providing a jittered reference signal to the non- linear circuit element (103) for attenuating the at least one spurious signal at the output.

Abstract translation: 频率合成器（100）包括：频率源，产生包括基于参考频率具有周期性的多个脉冲的参考信号（107）; 一个反馈回路，包括相位检测器电路（119），环路滤波器（120），在输出端（112）产生输出信号的受控振荡器（121）和环路除电路（122）; 在相位检测器电路（119）的输入处的非线性电路元件（103），其产生在输出端引起至少一个杂散信号的互调失真; 以及控制环路分割电路（122）和非线性电路元件（103）的控制器（106）。 频率合成器还包括抖动电路（101），其基于由控制器（106）提供给非线性电路元件（103）的参数来调整参考信号的一些脉冲的定时，从而提供一个 向非线性电路元件（103）抖动参考信号，用于衰减输出端的至少一个杂散信号。

公开(公告)号：WO2008085597A8

公开(公告)日：2008-09-25

申请号：PCT/US2007083386

申请日：2007-11-01

Applicant: MOTOROLA INC ,  GAILUS PAUL H ,  CHARASKA JOSEPH A

Inventor： GAILUS PAUL H ,  CHARASKA JOSEPH A

IPC: H03B5/12

CPC classification number: H03J3/20 ,  H03B2201/0208 ,  H03J2200/10

Abstract: A plurality of varactors are coupled (102) via a first electrode to a shared terminal that in turn can operably couple (103) to a source of control voltage. A second electrode for each varactor couples (107) to a corresponding switch, where each switch couples to at least two different voltage levels. So configured, the second electrode of each varactor can be individually connected to either of two voltage levels. This can be leveraged to control, in coarse steps, the overall aggregate effective capacitance presented by these components. At least some of these varactors can have differing corresponding capacitances, the specific values of which can be selected in order to facilitate relatively equal spacing and substantially equal rates of reactance change versus the control voltage value between aggregate-capacitive reactance ranges as correspond to differing settings for the switches at various levels for the control voltage source.

公开(公告)号：WO2007127574A3

公开(公告)日：2008-12-31

申请号：PCT/US2007065456

申请日：2007-03-29

Applicant: MOTOROLA INC ,  GAILUS PAUL H ,  CHARASKA JOSEPH A

Inventor： GAILUS PAUL H ,  CHARASKA JOSEPH A

IPC: H03D13/00

CPC classification number: H03D13/00 ,  H03L7/0891 ,  H03L7/1976

Abstract: A phase-frequency detector (110) is provided. The phase-frequency detector can include a frequency counter delay (147) for counting cycles of an output signal to generate a divided variable frequency delayed signal (FVd 146) having a time shift. A control stage (200) coupled to the output stage generates a pump up control signal (222) and a pump down control signal (234) in response to receiving the FVd signal, a divided variable frequency signal (FV 136), and a reference frequency signal (FR 106). The time shift provides an overlap region that allows both source (350) and sink (360) currents to be provided in phase lock. In phase lock, the duration of the pump up control signal approximates the duration of the pump down control signal within a linear region of operation.

Abstract translation: 提供了一个相位频率检测器（110）。 相位频率检测器可以包括用于对输出信号的周期进行计数以产生具有时移的分频可变频率延迟信号（FVd 146）的频率计数器延迟（147）。 耦合到输出级的控制级（200）响应于接收到FVd信号，分频可变频率信号（FV 136）和参考信号而产生泵浦控制信号（222）和抽空控制信号（234） 频率信号（FR 106）。 时移提供了一个重叠区域，允许在锁相中提供源极（350）和吸收（360）电流。 在锁相中，泵浦控制信号的持续时间近似于线性操作区域内的抽空控制信号的持续时间。

公开(公告)号：WO2006130333A2

公开(公告)日：2006-12-07

申请号：PCT/US2006/018713

申请日：2006-05-12

Applicant: MOTOROLA, INC. ,  GONZALEZ, Armando, J. ,  CHARASKA, Joseph, A. ,  DUBOV, Vadim ,  MARTIN, William, J.

Inventor： GONZALEZ, Armando, J. ,  CHARASKA, Joseph, A. ,  DUBOV, Vadim ,  MARTIN, William, J.

CPC classification number: H03L7/0898 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1976

Abstract: A system and method for reducing a transient response in a phase lock loop (PLL) (100) is disclosed. The system includes an adapt mode charge pump (204), a normal mode charge pump (206) and the use of controlled trickle currents (208), (210) applied to those charge pumps to minimize a transient response of the PLL (100).

Abstract translation: 公开了一种用于减小锁相环（PLL）（100）中的瞬态响应的系统和方法。 该系统包括适应模式电荷泵（204），正常模式电荷泵（206）以及施加到这些电荷泵的受控涓流（208），（210）的使用以最小化PLL（100）的瞬态响应， 。

公开(公告)号：WO2005109647A2

公开(公告)日：2005-11-17

申请号：PCT/US2005/008549

申请日：2005-03-14

Applicant: MOTOROLA, INC., A CORPORATION OF THE STATE OF DELAWARE ,  WILHITE, Jeffrey B., ,  CHARASKA, Joseph A., ,  GABATO, JR., Manuel P., ,  GAILUS, Paul H., ,  STENGEL, Robert E.,

Inventor： WILHITE, Jeffrey B., ,  CHARASKA, Joseph A., ,  GABATO, JR., Manuel P., ,  GAILUS, Paul H., ,  STENGEL, Robert E.,

IPC: H03L7/06

CPC classification number: H03L7/16 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0812

Abstract: A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

Abstract translation: 延迟锁定环路300，其包括：用于产生具有可调频率的时钟信号（322）的可调频率源（320） 调整和抽头选择控制器（310），用于根据第二频率确定第一频率，并使频率源将时钟信号的频率调整到基本上第一频率;第二频率是期望的频率 第一输出信号; 延迟线（330），被配置为接收用于产生多个相移时钟信号的时钟信号; 以及第一选择电路（370），用于接收多个相移时钟信号，并用于在调整和抽头选择控制器的控制下一次一个地选择第一个相移时钟信号序列，用于产生 第一输出信号具有基本上第二频率。

公开(公告)号：WO2008085597A2

公开(公告)日：2008-07-17

申请号：PCT/US2007083386

申请日：2007-11-01

Applicant: MOTOROLA INC ,  GAILUS PAUL H ,  CHARASKA JOSEPH A

Inventor： GAILUS PAUL H ,  CHARASKA JOSEPH A

IPC: H03B5/12

CPC classification number: H03J3/20 ,  H03B2201/0208 ,  H03J2200/10

Abstract: A plurality of varactors are coupled (102) via a first electrode to a shared terminal that in turn can operably couple (103) to a source of control voltage. A second electrode for each varactor couples (107) to a corresponding switch, where each switch couples to at least two different voltage levels. So configured, the second electrode of each varactor can be individually connected to either of two voltage levels. This can be leveraged to control, in coarse steps, the overall aggregate effective capacitance presented by these components. At least some of these varactors can have differing corresponding capacitances, the specific values of which can be selected in order to facilitate relatively equal spacing and substantially equal rates of reactance change versus the control voltage value between aggregate-capacitive reactance ranges as correspond to differing settings for the switches at various levels for the control voltage source.

Abstract translation: 多个变容二极管经由第一电极耦合（102）到共享端子，共享端子又可操作地耦合（103）到控制电压源。 用于每个变容二极管的第二电极将（107）耦合到相应的开关，其中每个开关耦合到至少两个不同的电压电平。 如此配置，每个变容二极管的第二电极可以单独连接到两个电压电平中的任一个。 这可以用来粗略地控制由这些组件提供的总体有效电容。 这些变容二极管中的至少一些可以具有不同的对应电容，其特定值可以被选择以便于相对于不同的设置来促进相对等间隔和基本相等的电抗变化率与聚集电容电抗范围之间的控制电压值 用于控制电压源的各种开关。

公开(公告)号：WO2006130333A3

公开(公告)日：2008-05-08

申请号：PCT/US2006018713

申请日：2006-05-12

Applicant: MOTOROLA INC ,  GONZALEZ ARMANDO J ,  CHARASKA JOSEPH A ,  DUBOV VADIM ,  MARTIN WILLIAM J

Inventor： GONZALEZ ARMANDO J ,  CHARASKA JOSEPH A ,  DUBOV VADIM ,  MARTIN WILLIAM J

IPC: H03L7/06

CPC classification number: H03L7/0898 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1976

Abstract: A system and method for reducing a transient response in a phase lock loop (PLL) (100) is disclosed. The system includes an adapt mode charge pump (204), a normal mode charge pump (206) and the use of controlled trickle currents (208), (210) applied to those charge pumps to minimize a transient response of the PLL (100).

Abstract translation: 公开了一种用于减小锁相环（PLL）（100）中的瞬态响应的系统和方法。 该系统包括适应模式电荷泵（204），正常模式电荷泵（206）以及施加到这些电荷泵的受控涓流（208），（210）的使用以最小化PLL（100）的瞬态响应， 。

公开(公告)号：WO2006039093A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/032542

申请日：2005-09-12

Applicant: MOTOROLA, INC. ,  GABATO, Manuel, P., Jr. ,  CHARASKA, Joseph, A. ,  GAILUS, Paul, H.

Inventor： GABATO, Manuel, P., Jr. ,  CHARASKA, Joseph, A. ,  GAILUS, Paul, H.

IPC: H03B21/00

CPC classification number: H03L7/0812 ,  H03K5/1504 ,  H03K2005/00032 ,  H03L7/07 ,  H03L7/16

Abstract: A DPC (200) that includes: a frequency source (20); a delay-locked loop (220) for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device (280) having a DPS (282) and a DAC (284) for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit (270) for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell (290) having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal (292) having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.

Abstract translation: DPC（200），其包括：频率源（20）; 延迟锁定环路（220），用于接收时钟信号并产生多个相移时钟信号; 具有DPS（282）和DAC（284）的控制装置（280），用于接收标识合成信号的期望频率的输入信号; 选择电路（270），用于接收多个相移时钟信号，选择相移时钟信号的序列并输出粗略的合成信号; 可变延迟单元（290），其具有耦合到选择电路以接收粗略合成信号的第一输入和耦合到控制装置的第二输入，用于接收微调调整信号以修改粗合成信号以产生合成信号 292）具有基本上所需的频率。 DPC还包括用于校准DPC的训练装置。

公开(公告)号：WO2005109647A3

公开(公告)日：2008-09-12

申请号：PCT/US2005008549

申请日：2005-03-14

Applicant: MOTOROLA INC ,  WILHITE JEFFREY B ,  CHARASKA JOSEPH A ,  GABATO JR MANUEL P ,  GAILUS PAUL H ,  STENGEL ROBERT E

Inventor： WILHITE JEFFREY B ,  CHARASKA JOSEPH A ,  GABATO MANUEL P JR ,  GAILUS PAUL H ,  STENGEL ROBERT E

IPC: H03L7/06 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081 ,  H03L7/16

CPC classification number: H03L7/16 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0812

Abstract: A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

Abstract translation: 延迟锁定环路300，其包括：用于产生具有可调频率的时钟信号（322）的可调频率源（320） 调整和抽头选择控制器（310），用于根据第二频率确定第一频率，并使频率源将时钟信号的频率调整到基本上第一频率;第二频率是期望的频率 第一输出信号; 延迟线（330），被配置为接收用于产生多个相移时钟信号的时钟信号; 以及第一选择电路（370），用于接收多个相移时钟信号，并用于在调整和抽头选择控制器的控制下一次一个地选择第一个相移时钟信号序列，用于产生 第一输出信号具有基本上第二频率。