公开(公告)号：WO2013016345A2

公开(公告)日：2013-01-31

申请号：PCT/US2012047991

申请日：2012-07-24

Applicant: INTEL CORP ,  SANKARAN RAJESH M ,  KOKER ALTUG ,  LANTZ PHILIP ,  MALLICK ASIT K ,  CROSSLAND JAMES B ,  NAVALE ADITVA ,  NEIGER GILBERT ,  ANDERSON ANDREW V

Inventor： SANKARAN RAJESH M ,  KOKER ALTUG ,  LANTZ PHILIP ,  MALLICK ASIT K ,  CROSSLAND JAMES B ,  NAVALE ADITVA ,  NEIGER GILBERT ,  ANDERSON ANDREW V

IPC: G06F12/10 ,  G06F15/80

CPC classification number: G06F12/1027 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/303 ,  G06F2212/682 ,  G06F2212/683

Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

Abstract translation: 公开了用于在多核系统中共享虚拟存储器的异构设备的有效TLB（转换后备缓冲器）击穿的方法和装置。 用于有效的TLB击倒的装置的实施例可以包括用于存储虚拟地址转换条目的TLB和与TLB耦合的存储器管理单元，以维护对应于虚拟地址转换条目的PASID（进程地址空间标识符）状态条目 。 PASID状态条目可以包括活动参考状态和惰性无效状态。 响应于从多核系统中的设备接收到PASID状态更新请求并且读取PASID状态条目的惰性无效状态，存储器管理单元可执行PASID状态条目的原子修改。 存储器管理单元可以在响应于相应的惰性无效化状态的激活之前向设备发送PASID状态更新响应以同步TLB条目。

公开(公告)号：WO2013101059A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067838

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  VAN DE VEN, Adriaan ,  PATEL, Baiju, V. ,  MALLICK, Asit, K. ,  NEIGER, Gilbert ,  COKE, James, S. ,  DIXON, Martin, G. ,  BRANDT, Jason, W.

Inventor： VAN DE VEN, Adriaan ,  PATEL, Baiju, V. ,  MALLICK, Asit, K. ,  NEIGER, Gilbert ,  COKE, James, S. ,  DIXON, Martin, G. ,  BRANDT, Jason, W.

IPC: G06F21/22 ,  G06F9/30

CPC classification number: G06F9/30189 ,  G06F9/30043 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1491

Abstract: Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.

Abstract translation: 公开了用于监督模式执行保护的装置和方法。 在一个实施例中，处理器包括访问存储器，执行硬件和控制逻辑的接口。 存储器中的区域是用户存储器。 执行硬件是执行指令。 当指令存储在用户存储器中并且处理器处于主管模式时，控制逻辑是防止执行硬件执行指令。

公开(公告)号：WO2014197310A1

公开(公告)日：2014-12-11

申请号：PCT/US2014/040209

申请日：2014-05-30

Applicant: INTEL CORPORATION ,  PATEL, Baiju V. ,  LI, Xiaoning ,  ANVIN, H. P. ,  MALLICK, Asit K. ,  NEIGER, Gilbert ,  CROSSLAND, James B. ,  OPFERMAN, Toby ,  KHARE, Atul A. ,  BRANDT, Jason W. ,  COKE, James S. ,  VAJDA, Brian L.

Inventor： PATEL, Baiju V. ,  LI, Xiaoning ,  ANVIN, H. P. ,  MALLICK, Asit K. ,  NEIGER, Gilbert ,  CROSSLAND, James B. ,  OPFERMAN, Toby ,  KHARE, Atul A. ,  BRANDT, Jason W. ,  COKE, James S. ,  VAJDA, Brian L.

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/145 ,  G06F8/434 ,  G06F9/30105 ,  G06F9/30134 ,  G06F21/52

Abstract: An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.

Abstract translation: 示例处理系统可以包括：下堆叠绑定寄存器，被配置为存储第一存储器地址，第一存储器地址识别经由堆栈段可寻址的存储器的下限; 上堆叠绑定寄存器，其被配置为存储第二存储器地址，所述第二存储器地址通过所述堆栈段识别所述存储器可寻址的上限; 并且通过将经由所述堆栈段访问的存储器地址与所述第一存储器地址和所述第二存储器地址中的至少一个进行比较来配置用于检测未授权堆栈枢转的堆栈边界检查逻辑。

公开(公告)号：WO2013016345A3

公开(公告)日：2013-01-31

申请号：PCT/US2012/047991

申请日：2012-07-24

Applicant: INTEL CORPORATION ,  SANKARAN, Rajesh M. ,  KOKER, Altug ,  LANTZ, Philip ,  MALLICK, Asit K. ,  CROSSLAND, James B. ,  NAVALE, Aditva ,  NEIGER, Gilbert ,  ANDERSON, Andrew V.

Inventor： SANKARAN, Rajesh M. ,  KOKER, Altug ,  LANTZ, Philip ,  MALLICK, Asit K. ,  CROSSLAND, James B. ,  NAVALE, Aditva ,  NEIGER, Gilbert ,  ANDERSON, Andrew V.

IPC: G06F12/10 ,  G06F15/80

Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.