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    Fuse structures, methods of making and using the same, and integrated circuits including the same
    3.
    发明授权
    Fuse structures, methods of making and using the same, and integrated circuits including the same 有权
    保险丝结构，制造和使用它们的方法以及包括其的集成电路

    公开(公告)号：US07704805B1

    公开(公告)日：2010-04-27

    申请号：US12012723

    申请日：2008-02-04

    Applicant: Chuan-Cheng Cheng ,  Shuhua Yu ,  Roawen Chen ,  Albert Wu

    Inventor： Chuan-Cheng Cheng ,  Shuhua Yu ,  Roawen Chen ,  Albert Wu

    IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/336

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

    Abstract translation: 保险丝结构，包括该结构的集成电路，以及使用该保险丝的结构和（重新）配置电路的方法。 熔丝结构通常包括（a）具有至少两个电耦合到其上的电路元件的导电结构，（b）导电结构上的电介质层，和（c）第一介电层和导电结构上的第一透镜， 以至少部分地将光聚焦到导电结构上。 制造该结构的方法通常包括以下步骤：（1）形成电耦合到第一和第二电路元件的导电结构，（2）在其上形成介电层，和（3）在电介质层上或之上形成透镜， 在导电结构之上，透镜被配置为至少部分地将光聚焦到导电结构上。 （重新）配置电路的方法通常包括以下步骤：（i）在电路表面上或附近照射足够的电气断开位于透镜下方的对应的第一保险丝的至少一个透镜，并且禁用电路的第一配置 ，以及（ii）在该电路表面上或其附近照射至少一个其他透镜，足以使位于该透镜下方的对应的第二保险丝电气断开并使电路能够进行第二配置。 该结构和方法有利地提供具有改善的可靠性和更小的芯片面积的熔丝结构，从而提高制造工艺的产量和每个晶片的模具数量（总和良好）。

    Method for simultaneous formation of integrated capacitor and fuse
    4.
    发明授权
    Method for simultaneous formation of integrated capacitor and fuse 有权
    同时形成集成电容器和保险丝的方法

    公开(公告)号：US06495426B1

    公开(公告)日：2002-12-17

    申请号：US09925694

    申请日：2001-08-09

    Applicant: Chuan-Cheng Cheng ,  Yauh-Ching Liu

    Inventor： Chuan-Cheng Cheng ,  Yauh-Ching Liu

    IPC: H01L2120

    CPC classification number: H01L23/5258 ,  H01L27/0676 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlying the first dielectric layer, a capacitor dielectric section overlying the first capacitor plate, and a fuse barrier section overlying and between the first and second fuse electrodes are formed simultaneously. In a conductive layer overlying the second dielectric layer, a second capacitor plate overlying the capacitor dielectric section, and a fuse overlying the fuse barrier section and contacting the first and second fuse electrodes are formed simultaneously. The capacitor dielectric section and the fuse barrier section may be defined simultaneously by selectively removing portions of the first dielectric layer during a single etching step. The second capacitor plate and the fuse may be defined simultaneously by selectively removing portions of the conductive layer during a single etching step. Thus, the invention provides for forming various structures of the capacitor and the fuse during the same photomask, patterning, and etching steps, thereby reducing fabrication cost and time.

    Abstract translation: 在集成电路器件中形成电容结构和熔丝结构的工艺包括在器件的第一介电层中形成第一电容器板和第一和第二熔丝电极。 在覆盖第一电介质层的第二电介质层中，同时形成覆盖第一电容器板的电容器介电部分和覆盖在第一和第二熔丝电极之间的熔丝阻挡部分。 在覆盖第二电介质层的导电层中，同时形成覆盖电容器介电部分的第二电容器板，以及覆盖熔丝阻挡部分并接触第一和第二熔丝电极的熔丝。 可以通过在单个蚀刻步骤期间选择性地去除第一介电层的部分来同时限定电容器介电部分和熔丝阻挡部分。 可以通过在单个蚀刻步骤期间选择性地去除导电层的部分来同时限定第二电容器板和熔丝。 因此，本发明提供了在相同的光掩模，图案化和蚀刻步骤期间形成电容器和熔丝的各种结构，从而降低制造成本和时间。

    Fuse structures, methods of making and using the same, and integrated circuits including the same
    9.
    发明授权
    Fuse structures, methods of making and using the same, and integrated circuits including the same 有权
    保险丝结构，制造和使用它们的方法以及包括其的集成电路

    公开(公告)号：US06940107B1

    公开(公告)日：2005-09-06

    申请号：US10734779

    申请日：2003-12-12

    Applicant: Chuan-Cheng Cheng ,  Shuhua Yu ,  Roawen Chen ,  Albert Wu

    Inventor： Chuan-Cheng Cheng ,  Shuhua Yu ,  Roawen Chen ,  Albert Wu

    IPC: H01L23/525 ,  H01L27/10

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

    Abstract translation: 保险丝结构，包括该结构的集成电路，以及使用该保险丝的结构和（重新）配置电路的方法。 熔丝结构通常包括（a）具有至少两个电耦合到其上的电路元件的导电结构，（b）导电结构上的电介质层，和（c）第一介电层和导电结构上的第一透镜， 以至少部分地将光聚焦到导电结构上。 制造该结构的方法通常包括以下步骤：（1）形成电耦合到第一和第二电路元件的导电结构，（2）在其上形成介电层，和（3）在电介质层上或之上形成透镜， 在导电结构之上，透镜被配置为至少部分地将光聚焦到导电结构上。 （重新）配置电路的方法通常包括以下步骤：（i）在电路表面上或附近照射足够的电气断开位于透镜下方的对应的第一保险丝的至少一个透镜，并且禁用电路的第一配置 ，以及（ii）在该电路表面上或其附近照射至少一个其他透镜，足以使位于该透镜下方的对应的第二保险丝电气断开并使电路能够进行第二配置。 该结构和方法有利地提供具有改善的可靠性和更小的芯片面积的熔丝结构，从而提高制造工艺的产量和每个晶片的模具数量（总和良好）。

    Low resistance metal interconnect lines and a process for fabricating them
    10.
    发明授权
    Low resistance metal interconnect lines and a process for fabricating them 有权
    低电阻金属互连线及其制造工艺

    公开(公告)号：US06815342B1

    公开(公告)日：2004-11-09

    申请号：US09996118

    申请日：2001-11-27

    Applicant: Chuan-cheng Cheng ,  Sethuraman Lakshminarayanan ,  Peter J. Wright ,  Hong Ying

    Inventor： Chuan-cheng Cheng ,  Sethuraman Lakshminarayanan ,  Peter J. Wright ,  Hong Ying

    IPC: H01L214763

    CPC classification number: H01L21/76838 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.

    Abstract translation: 本文描述了低电阻互连线及其制造方法。 IC制造工艺用于制造Al和Cu层的互连线。 Cu层比现有技术更薄，但与Al层结合时，聚集的Cu / Al电阻降低到与非常厚的Cu层相当的点，而没有额外的成本和产率问题 由于使用较厚的铜沉积引起。 用于记忆修复的保险丝也可以使用本发明教导的方法制造，只有该过程的变化很小。

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