公开(公告)号：WO2007137969A1

公开(公告)日：2007-12-06

申请号：PCT/EP2007/054941

申请日：2007-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  CLEVENGER, Lawrence ,  DALTON, Timothy, Joseph ,  HSU, Louis, Lu-Chen ,  RADENS, Carl, John ,  RAMACHANDRAN, Vidhya ,  WONG, Keith, Kwong Hon ,  YANG, Chih-Chao

Inventor： CLEVENGER, Lawrence ,  DALTON, Timothy, Joseph ,  HSU, Louis, Lu-Chen ,  RADENS, Carl, John ,  RAMACHANDRAN, Vidhya ,  WONG, Keith, Kwong Hon ,  YANG, Chih-Chao

IPC: H01L21/8242 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

Abstract: Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semico nductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

Abstract translation: 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

公开(公告)号：WO2006017600A3

公开(公告)日：2006-06-22

申请号：PCT/US2005027618

申请日：2005-08-04

Applicant: IBM ,  CHINTHAKINDI ANIL K ,  COOLBAUGH DOUGLAS D ,  RAMACHANDRAN VIDHYA ,  RASSEL ROBERT M

Inventor： CHINTHAKINDI ANIL K ,  COOLBAUGH DOUGLAS D ,  RAMACHANDRAN VIDHYA ,  RASSEL ROBERT M

IPC: H01L21/20

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L29/7833

Abstract: A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.

Abstract translation: FEOL / MEOL金属电阻（32）具有紧密的薄层电阻公差（约5％或更小），高电流密度（约0.5mA /微米或更大），比扩散电阻器更低的寄生效应， 提供比标准BEOL金属电阻器更低的TCR以及将这种金属电阻器结构（32）集成到CMOS技术中的各种方法。

公开(公告)号：WO2005034201A3

公开(公告)日：2007-12-06

申请号：PCT/US2004032405

申请日：2004-09-30

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interievel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interievel dielectric layer, atop surface of the bottom electrode co-planer with a top surface of the interievel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Abstract translation: 一种MIM电容器的方法和结构，所述结构包括：电子器件，包括：形成在半导体衬底上的电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的顶表面具有所述电介质层的顶表面; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

公开(公告)号：WO2005122245A3

公开(公告)日：2005-12-22

申请号：PCT/US2005/018521

申请日：2005-05-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COOLBAUGH, Douglas, D. ,  ESHUN, Ebenezer, E. ,  FEILCHENFELD, Natalie ,  GAUTSCH, Michael, L. ,  HE, Zhong-Xiang ,  MOON, Matthew, D. ,  RAMACHANDRAN, Vidhya ,  WATERHOUSE, Barbara

Inventor： COOLBAUGH, Douglas, D. ,  ESHUN, Ebenezer, E. ,  FEILCHENFELD, Natalie ,  GAUTSCH, Michael, L. ,  HE, Zhong-Xiang ,  MOON, Matthew, D. ,  RAMACHANDRAN, Vidhya ,  WATERHOUSE, Barbara

IPC: G03F7/00 ,  H01L21/20 ,  H01L21/8242

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer (102, 106) is formed above a lower conductor layer (100) and an upper conductor layer (104, 108) is formed above the dielectric layer. The invention then forms an etch stop layer (200) above the upper conductor layer and the dielectric layer, and forms a hardmask (202) (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist (300) is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

公开(公告)号：WO2005062380A1

公开(公告)日：2005-07-07

申请号：PCT/US2003/040003

申请日：2003-12-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HE, Zhong-Xiang ,  JOSEPH, J., Alvin ,  ORNER, A., Bradley ,  RAMACHANDRAN, Vidhya ,  ST. ONGE, A., Stephen ,  WANG, Ping-Chuan

Inventor： HE, Zhong-Xiang ,  JOSEPH, J., Alvin ,  ORNER, A., Bradley ,  RAMACHANDRAN, Vidhya ,  ST. ONGE, A., Stephen ,  WANG, Ping-Chuan

IPC: H01L23/48

CPC classification number: H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors (116) and a plurality of vertical bipolar transistors (118) positioned on a single substrate (110). The vertical bipolar transistors (118) are taller devices than the CMOS transistors (116). In this structure, a passivating layer (112) is positioned above the substrate (110), and between the vertical bipolar transistors (118) and the CMOS transistors (116). A wiring layer (120) is above the passivating layer (112). The vertical bipolar transistors (118) are in direct contact with the wiring layer (120) and the CMOS transistors (116) are connected to the wiring layer (114) by contacts extending through the passivating layer (112).

Abstract translation: 公开了一种集成电路结构的方法和结构，其包括位于单个衬底（110）上的多个互补金属氧化物半导体（CMOS）晶体管（116）和多个垂直双极晶体管（118）。 垂直双极晶体管（118）比CMOS晶体管（116）更高的器件。 在该结构中，钝化层（112）位于衬底（110）上方，并且位于垂直双极晶体管（118）和CMOS晶体管（116）之间。 布线层（120）位于钝化层（112）的上方。 垂直双极晶体管（118）与布线层（120）直接接触，CMOS晶体管（116）通过延伸穿过钝化层（112）的触点连接到布线层（114）。

公开(公告)号：WO2005034201A2

公开(公告)日：2005-04-14

申请号：PCT/US2004/032405

申请日：2004-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COOLBAUGH, Douglas, D. ,  ESHUN, Ebenezer, E. ,  GAMBINO, Jeffrey, P. ,  HE, Zhong-Xiang ,  RAMACHANDRAN, Vidhya

Inventor： COOLBAUGH, Douglas, D. ,  ESHUN, Ebenezer, E. ,  GAMBINO, Jeffrey, P. ,  HE, Zhong-Xiang ,  RAMACHANDRAN, Vidhya

IPC: H01L

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Abstract translation: 一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的顶面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

公开(公告)号：WO2005122245A2

公开(公告)日：2005-12-22

申请号：PCT/US2005018521

申请日：2005-05-26

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L27/01 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer (102, 106) is formed above a lower conductor layer (100) and an upper conductor layer (104, 108) is formed above the dielectric layer. The invention then forms an etch stop layer (200) above the upper conductor layer and the dielectric layer, and forms a hardmask (202) (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist (300) is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract translation: 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层（100）的上方形成介电层（102,106），在电介质层的上方形成上导体层（104,108）。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层（200），并在蚀刻停止层上形成硬掩模（202）（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上图案化光致抗蚀剂（300），其允许通过光刻胶蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：WO2006017600A2

公开(公告)日：2006-02-16

申请号：PCT/US2005/027618

申请日：2005-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHINTHAKINDI, Anil, K. ,  COOLBAUGH, Douglas, D. ,  RAMACHANDRAN, Vidhya ,  RASSEL, Robert, M.

Inventor： CHINTHAKINDI, Anil, K. ,  COOLBAUGH, Douglas, D. ,  RAMACHANDRAN, Vidhya ,  RASSEL, Robert, M.

IPC: H01L29/76 ,  H01L29/00

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L29/7833

Abstract: A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.

Abstract translation: 一种FEOL / MEOL金属电阻器（32），其具有紧密的薄层电阻容差（约5％或更小），高电流密度（约0.5mA /微米或更大的量级 ），比标准BEOL金属电阻器更低的寄生效应比扩散电阻器和更低的TCR，以及将这种金属电阻器结构（32）集成到CMOS技术中的各种方法。