公开(公告)号：WO2008116106A3

公开(公告)日：2008-09-25

申请号：PCT/US2008/057725

申请日：2008-03-20

Applicant: VIASAT, INC. ,  SCHUTZ, Robert, Lee ,  SCHWARTZ, Howell, B. ,  GIRKINS, Gregory, Scott ,  GRELL, Conrad, Claire ,  NG, Angie, Sheelan

Inventor： SCHUTZ, Robert, Lee ,  SCHWARTZ, Howell, B. ,  GIRKINS, Gregory, Scott ,  GRELL, Conrad, Claire ,  NG, Angie, Sheelan

IPC: H05K1/14

Abstract: A method for assembling a circuit card assembly (100) includes populating a plurality of components (110) on a top side of a component layer (105), performing component-level testing on at least one component of the plurality of components populated on the component layer, adhering a bonding layer (115) to a bottom side of the component layer, the bonding layer to facilitate bonding the component layer to an interconnect layer (120) and to provide connectivity between the plurality of components and the interconnect layer, and forming a single-sided circuit card assembly by adhering the interconnect layer to the bonding layer, the interconnect layer having a top side and a bottom side, the bonding layer adhered to the top side of the interconnect layer.

公开(公告)号：WO2008116106A2

公开(公告)日：2008-09-25

申请号：PCT/US2008057725

申请日：2008-03-20

Applicant: VIASAT INC ,  SCHUTZ ROBERT LEE ,  SCHWARTZ HOWELL B ,  GIRKINS GREGORY SCOTT ,  GRELL CONRAD CLAIRE ,  NG ANGIE SHEELAN

Inventor： SCHUTZ ROBERT LEE ,  SCHWARTZ HOWELL B ,  GIRKINS GREGORY SCOTT ,  GRELL CONRAD CLAIRE ,  NG ANGIE SHEELAN

CPC classification number: H05K1/144 ,  G01R31/2801 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/014 ,  H05K1/142 ,  H05K3/303 ,  H05K3/323 ,  H05K3/4602 ,  H05K3/4617 ,  H05K2201/041 ,  H05K2201/043 ,  H05K2201/09027 ,  H05K2201/10378 ,  H05K2203/162 ,  Y02P70/613 ,  H01L2924/00

Abstract: A method for assembling a circuit card assembly includes populating a plurality of components on a top side of a component layer, performing component-level testing on at least one component of the plurality of components populated on the component layer, adhering a bonding layer to a bottom side of the component layer, the bonding layer to facilitate bonding the component layer to an interconnect layer and to provide connectivity between the plurality of components and the interconnect layer, and forming a single-sided circuit card assembly by adhering the interconnect layer to the bonding layer, the interconnect layer having a top side and a bottom side, the bonding layer adhered to the top side of the interconnect layer.

Abstract translation: 一种用于组装电路卡组件的方法，包括在组件层的顶侧上填充多个组件，对组装层上填充的多个组件的至少一个组件执行组件级测试，将粘合层粘附到 组件层的底侧，接合层，以便于将组件层粘合到互连层并且提供多个部件和互连层之间的连接性，以及通过将互连层粘附到第一部分来形成单面电路卡组件 接合层，所述互连层具有顶侧和底侧，所述接合层粘附到所述互连层的顶侧。

公开(公告)号：WO2008116106A8

公开(公告)日：2009-06-11

申请号：PCT/US2008057725

申请日：2008-03-20

Applicant: VIASAT INC ,  SCHUTZ ROBERT LEE ,  SCHWARTZ HOWELL B ,  GIRKINS GREGORY SCOTT ,  GRELL CONRAD CLAIRE ,  NG ANGIE SHEELAN

Inventor： SCHUTZ ROBERT LEE ,  SCHWARTZ HOWELL B ,  GIRKINS GREGORY SCOTT ,  GRELL CONRAD CLAIRE ,  NG ANGIE SHEELAN

IPC: H05K1/14

CPC classification number: H05K1/144 ,  G01R31/2801 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/014 ,  H05K1/142 ,  H05K3/303 ,  H05K3/323 ,  H05K3/4602 ,  H05K3/4617 ,  H05K2201/041 ,  H05K2201/043 ,  H05K2201/09027 ,  H05K2201/10378 ,  H05K2203/162 ,  Y02P70/613 ,  H01L2924/00

Abstract: A method for assembling a circuit card assembly (100) includes populating a plurality of components (110) on a top side of a component layer (105), performing component-level testing on at least one component of the plurality of components populated on the component layer, adhering a bonding layer (115) to a bottom side of the component layer, the bonding layer to facilitate bonding the component layer to an interconnect layer (120) and to provide connectivity between the plurality of components and the interconnect layer, and forming a single-sided circuit card assembly by adhering the interconnect layer to the bonding layer, the interconnect layer having a top side and a bottom side, the bonding layer adhered to the top side of the interconnect layer.

Abstract translation: 一种用于组装电路卡组件（100）的方法，包括在组件层（105）的顶侧上填充多个组件（110），对组装层（105）上的多个组件的至少一个组件进行组件级测试 将结合层（115）粘合到所述部件层的底侧，所述接合层以便于将所述部件层粘合到互连层（120）并且提供所述多个部件和所述互连层之间的连接性，以及 通过将互连层粘附到接合层来形成单面电路卡组件，所述互连层具有顶侧和底侧，所述接合层粘附到互连层的顶侧。