公开(公告)号：EP1018160A1

公开(公告)日：2000-07-12

申请号：EP99939802.7

申请日：1999-01-29

Applicant: Grill, Alfred ,  Jahnes, Christopher Vincent ,  Patel, Vishnubhai Vitthalhai ,  Perraud, Laurent Claude

Inventor： Grill, Alfred ,  Jahnes, Christopher Vincent ,  Patel, Vishnubhai Vitthalhai ,  Perraud, Laurent Claude

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76832 ,  C23C16/325 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/31633 ,  H01L23/291 ,  H01L23/296 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/30 ,  H01L2924/00

Abstract: A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film (38, 44) which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film (38, 44), specific precursor materials having a ring structure are preferred.

公开(公告)号：WO2007089223A2

公开(公告)日：2007-08-09

申请号：PCT/US2006/001154

申请日：2006-01-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DIMITRAKOPOULOS, Christos, D. ,  GATES, Stephen, M. ,  GRILL, Alfred ,  LANE, Michael, W. ,  LINIGER, Eric, G. ,  LIU, Xiao, Hu ,  NGUYEN, Son, Van ,  NEUMAYER, Deborah, A. ,  SHAW, Thomas, M.

Inventor： DIMITRAKOPOULOS, Christos, D. ,  GATES, Stephen, M. ,  GRILL, Alfred ,  LANE, Michael, W. ,  LINIGER, Eric, G. ,  LIU, Xiao, Hu ,  NGUYEN, Son, Van ,  NEUMAYER, Deborah, A. ,  SHAW, Thomas, M.

IPC: H01L21/00

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract translation: 描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜 的氧和水各自小于10ppm。 还通过使用介电常数不大于2.8的方法描述材料。 本发明克服了低双轴应力低于46MPa的薄膜形成问题。

公开(公告)号：WO2004083495A3

公开(公告)日：2005-02-03

申请号：PCT/US2004008195

申请日：2004-03-17

Applicant: IBM ,  GATES STEPHEN M ,  GRILL ALFRED

Inventor： GATES STEPHEN M ,  GRILL ALFRED

IPC: C09C1/00 ,  H01L21/312 ,  H01L21/316 ,  B05D3/06 ,  B05D3/02 ,  B23B5/14 ,  B23B5/18 ,  H01L21/3105 ,  H05H1/46

CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02277 ,  H01L21/02304 ,  H01L21/02351 ,  H01L21/3122 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/249953 ,  Y10T428/249978 ,  H01L2924/00

Abstract: The present invention provides a multiphase, ultra low k film exhibiting improved elastic modulus and hardness, and various methods for forming the same. The multiphase, ultra low k dielectric film includes atoms of Si, C, O and H, represented by (104), (103), (102) and (101) respectively, has a dielectric constant of about 2.4 or less, nanosized pores or voids, an elastic modulus of about 5 or greater and a hardness of about 0.7 or greater. A preferred film includes atoms of Si, C, O and H, has a dielectric constant of about 2.2 or less, nanosized pores or voids, an elastic modulus of about 3 or greater and a hardness of about 0.3 or greater. These films consist of a first phase (100) of "host" matrix that is a random network of hydrogenated oxidize silicon carbon material (SiCOH), and a second phase (105) consisting essentially of C and H atoms.

Abstract translation: 本发明提供了具有改善的弹性模量和硬度的多相超低k膜及其形成方法。 多相超低k电介质膜分别由（104），（103），（102）和（101）表示的Si，C，O和H原子，介电常数约为2.4以下，纳米孔 或空隙，约5或更大的弹性模量和约0.7或更大的硬度。 优选的膜包括Si，C，O和H的原子，具有约2.2或更小的介电常数，纳米孔或空隙，约3或更大的弹性模量和约0.3或更大的硬度。 这些膜包括作为氢化氧化硅碳材料（SiCOH）的随机网络的第一相（100）“主体”基质和基本上由C和H原子组成的第二相（105）。

公开(公告)号：WO2012145079A1

公开(公告)日：2012-10-26

申请号：PCT/US2012/027709

申请日：2012-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COHEN, Guy ,  DIMITRAKOPOULOS, Christos D. ,  GRILL, Alfred

Inventor： COHEN, Guy ,  DIMITRAKOPOULOS, Christos D. ,  GRILL, Alfred

IPC: H01L29/15

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02636 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/1025 ,  H01L29/1606 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/775 ,  H01L29/785 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0558

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract translation: 从碳化硅（SiC）翅片或纳米线的模板提供包括平行石墨烯纳米带或沿着晶体取向的碳纳米管的半导体结构。 首先提供SiC翅片或纳米线，然后通过退火在石墨片或纳米线的暴露表面上形成石墨烯纳米带或碳纳米管。 在形成封闭碳纳米管的实施方案中，纳米线在退火之前被悬浮。 提供的石墨烯纳米带和碳纳米管的位置，取向和手性由相应的碳化硅翅片和形成它们的纳米线确定。

公开(公告)号：WO2009032488A1

公开(公告)日：2009-03-12

申请号：PCT/US2008/072955

申请日：2008-08-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GATES, Stephen M. ,  GRILL, Alfred ,  NGUYEN, Son ,  NITTA, Satyanarayana V. ,  SHAW, Thomas M.

Inventor： GATES, Stephen M. ,  GRILL, Alfred ,  NGUYEN, Son ,  NITTA, Satyanarayana V. ,  SHAW, Thomas M.

IPC: H01L21/70 ,  H01L23/532 ,  C23C16/00

CPC classification number: H01L23/5329 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A porous SiCOH (e.g., p-SiCOH) dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The inventive p-SiCOH dielectric film has more -(CHx) and less Si-O-H and Si-H bondings as compared to prior art p-SiCOH dielectric films. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si-OH (silanol) and Si-H groups at least within the pores has been reduced by about 90 % or less by the post treatment. Hence, the inventive p-SiCOH dielectric film has hydrophobicity improvement as compared with prior art p-SiCOH dielectric films. In the present invention, a p-SiCOH dielectric film is produced that is flexible since the pores of the inventive film include stabilized crosslinking -(CHx)- chains wherein x is 1,2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C-C double bond and/or at least one C-C triple bond.

Abstract translation: 通过在不饱和烃环境中后处理使多孔SiCOH（例如，p-SiCOH）介电膜在其中由增加的四面体应变引起的应力变化最小化。 与现有技术的p-SiCOH介电膜相比，本发明的p-SiCOH电介质膜具有更多的（（CH x））和更少的Si-O-H和Si-H键。 此外，提供稳定的pSiOCH电介质膜，其中至少在孔内的Si-OH（硅烷醇）和Si-H基团的量通过后处理减少约90％以下。 因此，与现有技术的p-SiCOH介电膜相比，本发明的p-SiCOH介电膜具有疏水性改善。 在本发明中，由于本发明薄膜的孔包括其中x为1,2或3的稳定的交联 - （CHx） - 链，因此制备柔性的p-SiCOH介电膜。 介电膜是利用包括至少一个C-C双键和/或至少一个C-C三键的气态环境的退火步骤进行的。

公开(公告)号：WO2005112095A1

公开(公告)日：2005-11-24

申请号：PCT/US2005/009820

申请日：2005-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GATES, Stephen M. ,  GRILL, Alfred ,  MEDEIROS, David R. ,  NEUMAYER, Deborah ,  NGUYEN, Son Van ,  PATEL, Vishnubhai V. ,  WANG, Xinhui

Inventor： GATES, Stephen M. ,  GRILL, Alfred ,  MEDEIROS, David R. ,  NEUMAYER, Deborah ,  NGUYEN, Son Van ,  PATEL, Vishnubhai V. ,  WANG, Xinhui

IPC: H01L21/312

CPC classification number: H01L21/3122 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/31695

Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition ("PECVD") process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.

Abstract translation: 公开了一种使用等离子体增强化学气相沉积（“PECVD”）工艺在平行板化学气相沉积工艺中制造包含Si，C，O和H原子的热稳定超低介电常数膜的方法。 还公开了通过该方法制备的包含热稳定的超低介电常数材料的绝缘层的电子器件。 为了制造热稳定的超低介电常数膜，使用特定的前体材料，例如硅烷衍生物，例如二乙氧基甲基硅烷（DEMS）和有机分子，例如双环庚二烯和环戊烯氧化物。

公开(公告)号：WO2005040453A2

公开(公告)日：2005-05-06

申请号：PCT/EP2004/052547

申请日：2004-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  GRILL, Alfred ,  NEUMAYER, Deborah ,  SINGH, Dinkar

Inventor： GRILL, Alfred ,  NEUMAYER, Deborah ,  SINGH, Dinkar

IPC: C23C16/26

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B2202/36 ,  C30B25/00 ,  C30B25/105 ,  C30B29/605 ,  H01J9/025 ,  H01J2201/30469 ,  Y10S977/843

Abstract: The diameter of carbon nanotubes grown by chemical vapor deposition is controlled independent of the catalyst size by controlling the residence time of reactive gases in the reactor.

Abstract translation: 通过控制反应气体在反应器中的停留时间来控制通过化学气相沉积生长的碳纳米管的直径与催化剂尺寸无关。

公开(公告)号：WO2005083750A3

公开(公告)日：2005-10-27

申请号：PCT/US2005005570

申请日：2005-02-22

Applicant: IBM ,  CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

Inventor： CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

IPC: H01L31/101

CPC classification number: H01L31/101

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n-­and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

Abstract translation: 本发明解决了创建与Si CMOS技术兼容的高速，高效率光电探测器的问题。 该结构由薄SOI衬底上的Ge吸收层组成，并利用隔离区，交替的n型和p型触点以及低电阻表面电极。 该器件利用掩埋绝缘层隔离底层衬底中产生的载流子，通过利用Ge吸收层在广谱上获得高量子效率，利用薄吸收层和窄电极间距实现低电压操作，以及兼容性 凭借其平面结构和使用IV族吸收材料而具有CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上直接生长Ge，并且随后进行热退火以实现高质量的吸收层。 该方法限制了可用于相互扩散的Si的量，由此允许Ge层退火而不会导致Ge层基本上被下面的Si稀释。

公开(公告)号：WO2004083495A2

公开(公告)日：2004-09-30

申请号：PCT/US2004/008195

申请日：2004-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GATES, Stephen, M. ,  GRILL, Alfred

Inventor： GATES, Stephen, M. ,  GRILL, Alfred

IPC: C30B

CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02277 ,  H01L21/02304 ,  H01L21/02351 ,  H01L21/3122 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/249953 ,  Y10T428/249978 ,  H01L2924/00

Abstract: The present invention provides a multiphase, ultra low k film which exhibits improved elastic modulus and hardness as well as various methods for forming the same. The multiphase, ultra low k dielectric film includes atoms of Si, C, 0 and H, has a dielectric constant of about 2.4 or less, nanosized pores or voids, an elastic modulus of about 5 or greater and a hardness of about 0.7 or greater. A preferred multiphase, ultra low k dielectric film includes atoms of Si, C, 0 and H, has a dielectric constant of about 2.2 or less, nanosized pores or voids, an elastic modulus of about 3 or greater and a hardness of about 0.3 or greater.

Abstract translation: 本发明提供了一种多相超低k膜，其具有改进的弹性模量和硬度以及其形成方法。 多相超低k电介质膜包括Si，C，O和H的原子，介电常数约为2.4或更小，纳米孔或空隙，弹性模量约5或更大，硬度约为0.7或更大 。 优选的多相超低k电介质膜包括Si，C，O和H的原子，具有约2.2以下的介电常数，纳米孔或空隙，约3以上的弹性模量和约0.3的硬度， 更大。

公开(公告)号：WO2004047150A3

公开(公告)日：2004-06-24

申请号：PCT/US0336969

申请日：2003-11-19

Applicant: IBM ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

Inventor： CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/26506 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/7624 ,  H01L21/76251 ,  Y10S438/933

Abstract: A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 10 cm . The approach begins with the growth of a pseudomorphic or nearlypseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operatiing with this method is dislocation nucleation at He-inducedplatelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

Abstract translation: 在Si或绝缘体上硅（SOI）衬底上获得薄（小于300nm）应变弛豫Si1-xGex缓冲层的方法。 这些缓冲层具有失配位错的均匀分布，其缓解了应变，表面光滑平滑，以及低穿透位错（TD）密度，即小于10 6 cm 2。 该方法开始于伪晶体或近似假晶Si1-xGex层的生长，即，不具有失配位错的层，然后将其注入He或其它轻元素，随后退火以实现实质的应变弛豫。 用这种方法操作的非常有效的应变松弛机理是位于Si（001）表面Si / Si1-xGex界面以下的He诱导的电镀层（不是气泡）的位错成核。