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    ULTRA LOW K (ULK) SICOH FILM AND METHOD
    1.
    发明申请
    ULTRA LOW K (ULK) SICOH FILM AND METHOD 审中-公开
    超低K（ULK）SICOH薄膜和方法

    公开(公告)号：WO2004083495A3

    公开(公告)日：2005-02-03

    申请号：PCT/US2004008195

    申请日：2004-03-17

    Applicant: IBM ,  GATES STEPHEN M ,  GRILL ALFRED

    Inventor： GATES STEPHEN M ,  GRILL ALFRED

    IPC: C09C1/00 ,  H01L21/312 ,  H01L21/316 ,  B05D3/06 ,  B05D3/02 ,  B23B5/14 ,  B23B5/18 ,  H01L21/3105 ,  H05H1/46

    CPC classification number: H01L21/31695 ,  H01L21/02126 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02277 ,  H01L21/02304 ,  H01L21/02351 ,  H01L21/3122 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/249953 ,  Y10T428/249978 ,  H01L2924/00

    Abstract: The present invention provides a multiphase, ultra low k film exhibiting improved elastic modulus and hardness, and various methods for forming the same. The multiphase, ultra low k dielectric film includes atoms of Si, C, O and H, represented by (104), (103), (102) and (101) respectively, has a dielectric constant of about 2.4 or less, nanosized pores or voids, an elastic modulus of about 5 or greater and a hardness of about 0.7 or greater. A preferred film includes atoms of Si, C, O and H, has a dielectric constant of about 2.2 or less, nanosized pores or voids, an elastic modulus of about 3 or greater and a hardness of about 0.3 or greater. These films consist of a first phase (100) of "host" matrix that is a random network of hydrogenated oxidize silicon carbon material (SiCOH), and a second phase (105) consisting essentially of C and H atoms.

    Abstract translation: 本发明提供了具有改善的弹性模量和硬度的多相超低k膜及其形成方法。 多相超低k电介质膜分别由（104），（103），（102）和（101）表示的Si，C，O和H原子，介电常数约为2.4以下，纳米孔 或空隙，约5或更大的弹性模量和约0.7或更大的硬度。 优选的膜包括Si，C，O和H的原子，具有约2.2或更小的介电常数，纳米孔或空隙，约3或更大的弹性模量和约0.3或更大的硬度。 这些膜包括作为氢化氧化硅碳材料（SiCOH）的随机网络的第一相（100）“主体”基质和基本上由C和H原子组成的第二相（105）。

    INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME
    4.
    发明申请
    INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME 审中-公开
    具有蘑菇状氧化物覆盖层的互连结构及用于制造相同结构的方法

    公开(公告)号：WO2011084667A2

    公开(公告)日：2011-07-14

    申请号：PCT/US2010060933

    申请日：2010-12-17

    Applicant: IBM ,  NGUYEN SON VAN ,  GRILL ALFRED ,  HAIGH THOMAS J ,  SHOBHA HOSADURGA ,  VO TUAN A

    Inventor： NGUYEN SON VAN ,  GRILL ALFRED ,  HAIGH THOMAS J ,  SHOBHA HOSADURGA ,  VO TUAN A

    IPC: H01L21/768 ,  H01L21/28

    CPC classification number: H01L21/76849 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76867

    Abstract: An interconnect structure is provided that includes a dielectric material (52) having a dielectric constant of 4.0 or less and including a plurality of conductive features (56) embedded therein. The dielectric material (52) has an upper surface that is located beneath an upper surface of each of the plurality of conductive features (56). A first dielectric cap (58) is located on the upper surface of the dielectric material (52) and extends onto at least a portion of the upper surface of each of the plurality of conductive features (56). As shown, the first dielectric cap (58) forms an interface (59) with each of the plurality of conductive features (56) that is opposite to an electrical field that is generated by neighboring conductive features. The inventive structure also includes a second dielectric cap (60) located on an exposed portion of the upper surface of each of the plurality of conductive features (56) not covered with the first dielectric cap (58). The second dielectric cap (60) further covers on an exposed surface of the first dielectric cap (58).

    Abstract translation: 提供了一种互连结构，其包括介电常数为4.0或更小并且包括嵌入其中的多个导电部件（56）的介电材料（52）。 介电材料（52）具有位于多个导电部件（56）中的每一个的上表面下方的上表面。 第一电介质帽（58）位于电介质材料（52）的上表面上并且延伸到多个导电部件（56）中的每一个的上表面的至少一部分上。 如所示，第一电介质帽（58）与多个导电特征（56）中的每一个形成与由相邻导电特征产生的电场相反的界面（59）。 本发明的结构还包括位于未被第一电介质帽（58）覆盖的多个导电部件（56）中的每一个的上表面的暴露部分上的第二电介质帽（60）。 第二电介质帽（60）还覆盖在第一电介质帽（58）的暴露表面上。

    STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE Ge-ON-INSULATOR PHOTODETECTOR
    5.
    发明申请
    STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE Ge-ON-INSULATOR PHOTODETECTOR 审中-公开
    高速CMOS兼容绝缘栅双极型晶体管的结构和制作方法

    公开(公告)号：WO2005083750A3

    公开(公告)日：2005-10-27

    申请号：PCT/US2005005570

    申请日：2005-02-22

    Applicant: IBM ,  CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

    Inventor： CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

    IPC: H01L31/101

    CPC classification number: H01L31/101

    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n-­and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

    Abstract translation: 本发明解决了创建与Si CMOS技术兼容的高速，高效率光电探测器的问题。 该结构由薄SOI衬底上的Ge吸收层组成，并利用隔离区，交替的n型和p型触点以及低电阻表面电极。 该器件利用掩埋绝缘层隔离底层衬底中产生的载流子，通过利用Ge吸收层在广谱上获得高量子效率，利用薄吸收层和窄电极间距实现低电压操作，以及兼容性 凭借其平面结构和使用IV族吸收材料而具有CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上直接生长Ge，并且随后进行热退火以实现高质量的吸收层。 该方法限制了可用于相互扩散的Si的量，由此允许Ge层退火而不会导致Ge层基本上被下面的Si稀释。

    RELAXED SiGe LAYERS ON Si OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING
    6.
    发明申请
    RELAXED SiGe LAYERS ON Si OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING 审中-公开
    通过离子植入和热退火在Si或硅绝缘体衬底上放置SiGe层

    公开(公告)号：WO2004047150A3

    公开(公告)日：2004-06-24

    申请号：PCT/US0336969

    申请日：2003-11-19

    Applicant: IBM ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

    Inventor： CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

    IPC: H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/26506 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/7624 ,  H01L21/76251 ,  Y10S438/933

    Abstract: A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 10 cm . The approach begins with the growth of a pseudomorphic or nearlypseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operatiing with this method is dislocation nucleation at He-inducedplatelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

    Abstract translation: 在Si或绝缘体上硅（SOI）衬底上获得薄（小于300nm）应变弛豫Si1-xGex缓冲层的方法。 这些缓冲层具有失配位错的均匀分布，其缓解了应变，表面光滑平滑，以及低穿透位错（TD）密度，即小于10 6 cm 2。 该方法开始于伪晶体或近似假晶Si1-xGex层的生长，即，不具有失配位错的层，然后将其注入He或其它轻元素，随后退火以实现实质的应变弛豫。 用这种方法操作的非常有效的应变松弛机理是位于Si（001）表面Si / Si1-xGex界面以下的He诱导的电镀层（不是气泡）的位错成核。

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