PROCESSES AND INTEGRATED SYSTEMS FOR ENGINEERING A SUBSTRATE SURFACE FOR METAL DEPOSITION
    1.
    发明申请
    PROCESSES AND INTEGRATED SYSTEMS FOR ENGINEERING A SUBSTRATE SURFACE FOR METAL DEPOSITION 审中-公开
    用于工程化金属沉积基板表面的工艺和集成系统

    公开(公告)号:WO2008027216A9

    公开(公告)日:2008-05-22

    申请号:PCT/US2007018270

    申请日:2007-08-17

    Abstract: The embodiments provide processes and integrated systems that produce a metal-to-metal or a silicon-to-metal interface to enhance electro-migration performance, to provide lower metal resistivity, and to improve metal-to-metal or silicon-to-metal interfacial adhesion for copper interconnects. An exemplary method of preparing a substrate surface to selectively deposit a thin layer of a cobalt-alloy material on a copper surface of in an integrated system to improve electromigration performance of a copper interconnect is provided. The method includes removing contaminants and metal oxides from the substrate surface in the integrated system, and reconditioning the substrate surface using a reducing environment after removing contaminants and metal oxides in the integrated system. The method also includes selectively depositing the thin layer of cobalt-alloy material on the copper surface of the copper interconnect in the integrated system after reconditioning the substrate surface. System to practice the exemplary method described above are also provided.

    Abstract translation: 这些实施例提供了产生金属对金属或硅 - 金属界面以提高电迁移性能,提供较低金属电阻率以及改善金属对金属或硅 - 金属的过程和集成系统 铜互连的界面粘合。 提供了一种制备衬底表面以在集成系统的铜表面上选择性地沉积钴合金材料薄层以提高铜互连的电迁移性能的示例性方法。 该方法包括从集成系统中的衬底表面去除污染物和金属氧化物,并且在去除集成系统中的污染物和金属氧化物之后,使用还原环境来修复衬底表面。 该方法还包括在修复基板表面之后,在集成系统中的铜互连的铜表面上选择性地沉积钴合金材料的薄层。 还提供了用于实践上述示例性方法的系统。

    CONTROLLED AMBIENT SYSTEM FOR INTERFACE ENGINEERING
    2.
    发明申请
    CONTROLLED AMBIENT SYSTEM FOR INTERFACE ENGINEERING 审中-公开
    用于界面工程的控制环境系统

    公开(公告)号:WO2008027386A2

    公开(公告)日:2008-03-06

    申请号:PCT/US2007/018924

    申请日:2007-08-28

    Abstract: A cluster architecture and methods for processing a substrate are disclosed. The cluster architecture includes a lab-ambient controlled transfer module that is coupled to one or more wet substrate processing modules. The lab-ambient controlled transfer module and the one or more wet substrate processing modules are configured to manage a first ambient environment. A vacuum transfer module that is coupled to the lab-ambient controlled transfer module and one or more plasma processing modules is also provided. The vacuum transfer module and the one or more plasma processing modules are configured to manage a second ambient environment. And, a controlled ambient transfer module that is coupled to the vacuum transfer module and one or more ambient processing modules is also included. The controlled ambient transfer module and the one or more ambient processing modules are configured to manage a third ambient environment. The cluster architecture therefore enables controlled processing of the substrate in either the first, second or third ambient environments, as well as during associated transitions. The embodiments also provide for efficient methods for filling a trench of a substrate.

    Abstract translation: 公开了用于处理衬底的簇结构和方法。 集群架构包括耦合到一个或多个湿式衬底处理模块的实验室环境受控传输模块。 实验室环境控制传递模块和一个或多个湿式衬底处理模块被配置为管理第一环境环境。 还提供耦合到实验室环境受控传输模块和一个或多个等离子体处理模块的真空传输模块。 真空转移模块和一个或多个等离子体处理模块被配置成管理第二周边环境。 并且,还包括耦合到真空传输模块和一个或多个环境处理模块的受控环境转移模块。 受控环境传输模块和一个或多个环境处理模块被配置为管理第三环境环境。 因此,集群架构使得能够在第一,第二或第三环境环境中以及在相关联的转换期间对衬底进行受控处理。 这些实施例还提供了用于填充衬底的沟槽的有效方法。

    WINDOW PROTECTOR FOR SPUTTER ETCHING OF METAL LAYERS
    4.
    发明申请
    WINDOW PROTECTOR FOR SPUTTER ETCHING OF METAL LAYERS 审中-公开
    用于金属层溅射器的窗户保护器

    公开(公告)号:WO2006071816A2

    公开(公告)日:2006-07-06

    申请号:PCT/US2005/046930

    申请日:2005-12-22

    CPC classification number: H01J37/321 C23F4/00 H01J37/32477

    Abstract: An inductively coupled plasma processing apparatus includes a chamber (100) having a top opening. A window (16) seals the top opening of the chamber, and the window has an inner surface that is exposed to an internal region of the chamber. A window protector (20) for protecting the inner surface of the window is disposed within the chamber. The window protector (20) is configured to prevent conductive etch byproducts from being deposited on the inner surface of the window in the form of a continuous loop. In one alternative embodiment, a plurality of window protectors (20') is affixed to the inner surface of the window. In another embodiment, the window has a plurality of T-shaped or dovetail slots formed therein. In yet another embodiment, a plurality of rectangular slots is formed in the window and a window protector having corresponding slots is mounted against the inner surface of the window.

    Abstract translation: 电感耦合等离子体处理装置包括具有顶部开口的腔室(100)。 窗口(16)密封室的顶部开口,并且窗口具有暴露于室的内部区域的内表面。 用于保护窗的内表面的窗保护件(20)设置在室内。 窗保护器(20)被配置为防止导电蚀刻副产物以连续环形式沉积在窗的内表面上。 在一个替代实施例中,多个窗保护器(20')固定到窗的内表面。 在另一个实施例中,窗口具有形成在其中的多个T形或燕尾槽。 在另一个实施例中,在窗口中形成多个矩形槽,并且具有相应槽的窗保护器安装在窗的内表面上。

    APPARATUS AND METHODS FOR MINIMIZING ARCING IN A PLASMA PROCESSING CHAMBER

    公开(公告)号:WO2003096765A3

    公开(公告)日:2003-11-20

    申请号:PCT/US2003/013597

    申请日:2003-05-01

    Abstract: A plasma processing chamber for processing a substrate to form electronic components thereon is disclosed. The plasma processing chamber includes a plasma-facing component (602) having a plasma-facing surface oriented toward plasma in the plasma processing chamber during processing of the substrate, the plasma-facing component being electrically isolated from a ground terminal. The plasma processing chamber further includes a grounding arrangement (600) coupled to the plasma-facing component, the grounding arrangement including a first resistance circuit (610) disposed in a first current path between the plasma-facing component and the ground terminal. The grounding arrangement further includes a RF filter arrangement (604, 610) disposed in at least one other current path between the plasma-facing component and the ground terminal, wherein a resistance value of the first resistance circuit is selected to substantially eliminate arcing between the plasma and the plasma-facing component during the processing of the substrate.

    APPARATUS AND METHODS FOR MINIMIZING ARCING IN A PLASMA PROCESSING CHAMBER
    6.
    发明申请
    APPARATUS AND METHODS FOR MINIMIZING ARCING IN A PLASMA PROCESSING CHAMBER 审中-公开
    用于最小化等离子体加工室中的ARCING的装置和方法

    公开(公告)号:WO03096765A2

    公开(公告)日:2003-11-20

    申请号:PCT/US0313597

    申请日:2003-05-01

    CPC classification number: H01J37/32477 H01J37/32623

    Abstract: A plasma processing chamber for processing a substrate to form electronic components thereon is disclosed. The plasma processing chamber includes a plasma-facing component having a plasma-facing surface oriented toward plasma in the plasma processing chamber during processing of the substrate, the plasma-facing component being electrically isolated from a ground terminal. The plasma processing chamber further includes a grounding arrangement coupled to the plasma-facing component, the grounding arrangement including a first resistance circuit disposed in a first current path between the plasma-facing component and the ground terminal. The grounding arrangement further includes a RF filter arrangement disposed in at least one other current path between the plasma-facing component and the ground terminal, wherein a resistance value of the first resistance circuit is selected to substantially eliminate arcing between the plasma and the plasma-facing component during the processing of the substrate.

    Abstract translation: 公开了一种用于处理基板以在其上形成电子部件的等离子体处理室。 等离子体处理室包括在处理基板期间在等离子体处理室中具有朝向等离子体的等离子体面向表面的等离子体面向部件,等离子体面向部件与接地端子电隔离。 等离子体处理室还包括耦合到等离子体面向部件的接地装置,接地装置包括设置在等离子体面向部件和接地端子之间的第一电流路径中的第一电阻电路。 接地装置还包括设置在等离子体面向部件和接地端子之间的至少一个其它电流通路中的RF滤波器装置,其中选择第一电阻电路的电阻值以基本上消除等离子体和等离子体 - 在处理基板期间面对部件。

    WINDOW PROTECTOR FOR SPUTTER ETCHING OF METAL LAYERS
    8.
    发明申请
    WINDOW PROTECTOR FOR SPUTTER ETCHING OF METAL LAYERS 审中-公开
    用于金属层溅射器的窗户保护器

    公开(公告)号:WO2006071816A3

    公开(公告)日:2007-02-22

    申请号:PCT/US2005046930

    申请日:2005-12-22

    CPC classification number: H01J37/321 C23F4/00 H01J37/32477

    Abstract: An inductively coupled plasma processing apparatus includes a chamber (100) having a top opening. A window (16) seals the top opening of the chamber, and the window has an inner surface that is exposed to an internal region of the chamber. A window protector (20) for protecting the inner surface of the window is disposed within the chamber. The window protector (20) is configured to prevent conductive etch byproducts from being deposited on the inner surface of the window in the form of a continuous loop. In one alternative embodiment, a plurality of window protectors (20') is affixed to the inner surface of the window. In another embodiment, the window has a plurality of T-shaped or dovetail slots formed therein. In yet another embodiment, a plurality of rectangular slots is formed in the window and a window protector having corresponding slots is mounted against the inner surface of the window.

    Abstract translation: 电感耦合等离子体处理装置包括具有顶部开口的室(100)。 窗口(16)密封室的顶部开口,并且窗口具有暴露于室的内部区域的内表面。 用于保护窗的内表面的窗保护器(20)设置在室内。 窗保护器(20)被配置为防止导电蚀刻副产物以连续环形式沉积在窗的内表面上。 在一个替代实施例中,多个窗保护器(20')固定到窗的内表面。 在另一个实施例中,窗口具有形成在其中的多个T形或燕尾槽。 在另一个实施例中,在窗口中形成多个矩形槽,并且具有相应槽的窗保护器安装在窗的内表面上。

    METHOD OF DETERMINING THE CORRECT AVERAGE BIAS COMPENSATION VOLTAGE DURING A PLASMA PROCESS
    9.
    发明申请
    METHOD OF DETERMINING THE CORRECT AVERAGE BIAS COMPENSATION VOLTAGE DURING A PLASMA PROCESS 审中-公开
    在等离子体过程中确定正确的平均偏置补偿电压的方法

    公开(公告)号:WO2006004744A2

    公开(公告)日:2006-01-12

    申请号:PCT/US2005/022914

    申请日:2005-06-28

    Abstract: A method for removing a substrate that is attached to a bipolar electrostatic chuck (ESC) by application of a bipolar ESC voltage is provided which includes discontinuing the bipolar ESC voltage after processing a current substrate, and determining a monopolar component error of the processing. The method also includes correcting the monopolar component error for a subsequent substrate.

    Abstract translation: 提供了一种通过施加双极ESC电压来去除附着于双极静电吸盘(ESC)的基板的方法,其包括在处理当前基板之后中止双极ESC电压,并且确定 处理的单极分量误差。 该方法还包括纠正后续衬底的单极分量误差。

Patent Agency Ranking