Abstract:
A method and an apparatus for translating a virtual address (305) into a physical address (315) in a multiple region virtual memory environment. In one embodiment, a translation lookside buffer (TLB) (313) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) (325) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit (311) associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit (319) are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.
Abstract:
The invention disclosed herein is a system and method for testing integrated circuit devices, including memory chips. The devices under test are subject to behavioural testing, in which a copy of signals in an application system is directed to the device under test, or to an electronic component connected to the device under test. This permits the device under test to be tested under the operating conditions of the application system, which is preferably similar to the actual application environment in which the device under test will ultimately be used. Conventional tests, including pattern testing and/or parametric tests, may also be performed on devices under test, if desired.
Abstract:
A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle (step 510), with the branch instructions ordered last in the sequence (step 520). The bundled instructions are transferred to execution units indicated by a template field (step 530) that is associated with the bundle. The first branch instruction in the bundle's execution sequence that is resolved taken is determined (step 540), and retirement of subsequent instructions in the execution sequence is suppressed (step 550).
Abstract:
A method and apparatus for dynamically predicting the outcome and the target address of a multiple-target branch instruction, where the multiple-target branch instruction contains at least two potential target addresses, not including the fall through address. In addition, this method and apparatus can also be used to predict multiple single-target branches simultaneously. The apparatus stores information indicating the outcome of previous executions and predictions of the multiple-target branch instruction in a branch prediction table. In addition, multiple target addresses (at least two) are associated with the multiple-target branch instruction. Using the information indicating the outcome of the previous execution of the multiple-target branch instruction, the apparatus predicts the outcome of a next execution of the multiple-target branch instruction, and predicts which, if any, of the target addresses associated with the multiple-target branch instruction, will be taken.
Abstract:
A method and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occurs. According to one aspect of the invention, a machine-readable medium having stored thereon data representing sequences of instructions (380) is described. When executed by a computer system the sequences of instructions (380) cause the computer system to perform a series of steps comprising preloading (384) one of a set of registers data retrieved from a memory starting at a first address, and storing memory conflict information (390) representing the first address. If a memory conflict has occurred between said first and second addresses, then one of the registers (350) is reloaded with the data located at the first address.
Abstract:
A lamp color temperature change structure includes a lamp holder, a light source on the lamp holder, a lift unit in front of the light source, and a colored lens mounted to the lift unit. The colored lens is movable and driven by the lift unit to a first position which is away from the front of the light source or a second position which is in front of the light source. The user can select the light from the light source to radiate toward the front of the lamp holder or penetrate the colored lens to generate a color temperature change and then radiate toward the front of the lamp holder according to different environment conditions.
Abstract:
A device for changing lamp color temperature includes a lamp holder installed therein with a luminous source. A colored lens is set in front of the luminous source and a rotary mechanism is connected with the colored lens. The rotary mechanism functions to drive the colored lens to rotate to a first position where the colored lens is far away from the luminous source and to a second position where the colored lens obstructs the front side of the luminous source. By so designing, a user can adjust the position of the colored lens and choose either to let the light emitted by the luminous source project directly or to let the light first pass through the colored lens to change color temperature and then project, thus able to adjust lamp color temperature in accordance with various environments.
Abstract:
A lamp color temperature change structure includes a lamp holder, a light source on the lamp holder, a lift unit in front of the light source, and a colored lens mounted to the lift unit. The colored lens is movable and driven by the lift unit to a first position which is away from the front of the light source or a second position which is in front of the light source. The user can select the light from the light source to radiate toward the front of the lamp holder or penetrate the colored lens to generate a color temperature change and then radiate toward the front of the lamp holder according to different environment conditions.
Abstract:
A method and an apparatus for translating a virtual address into a physical address in a multiple region virtual memory environment. In one embodiment, a translation lookside buffer (TLB) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.