公开(公告)号：WO9821712A3

公开(公告)日：1998-07-09

申请号：PCT/US9720610

申请日：1997-11-12

Applicant: IDEA CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY NEIL

IPC: G06F12/10 ,  G11B

CPC classification number: G06F12/1036 ,  G06F2212/681

Abstract: A method and an apparatus for translating a virtual address (305) into a physical address (315) in a multiple region virtual memory environment. In one embodiment, a translation lookside buffer (TLB) (313) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) (325) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit (311) associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit (319) are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.

公开(公告)号：EP1027656A4

公开(公告)日：2001-04-11

申请号：EP97946926

申请日：1997-11-12

Applicant: IDEA CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY NEIL

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F2212/681

Abstract: A method and an apparatus for translating a virtual address into a physical address in a multiple region virtual memory environment. In one embodiment, a translation lookside buffer (TLB) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.

公开(公告)号：AU5200998A

公开(公告)日：1998-06-03

申请号：AU5200998

申请日：1997-11-12

Applicant: IDEA CORP

Inventor： YAMADA KOICHI ,  HAMMOND GARY NEIL

IPC: G06F12/10 ,  G06F13/00

Abstract: The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.