公开(公告)号：WO1998014867A1

公开(公告)日：1998-04-09

申请号：PCT/US1997012610

申请日：1997-07-17

Applicant: IDEA CORPORATION

Inventor： IDEA CORPORATION ,  CALL, Josef, R. ,  MORRISON, Michael, J.

IPC: G06F09/38

CPC classification number: G06F9/3838 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A scheduling unit is described for scheduling an execution order of a first instruction of a first type (503) and a second instruction of a second type (506) in an instruction stream where the second instruction precedes the first instruction. The scheduling unit comprises a table that records address component identifiers corresponding to the second instructions (503). An address comparator is coupled to the table. The address comparator compares address component identifiers that corresponds to the first instruction with address component identifiers on the table (504). The scheduling unit schedules the first instruction to be executed ahead of the second instruction when the address component identifiers differ from the address component identifiers on the table (506).

Abstract translation: 描述了调度单元，用于在第二指令在第一指令之前的指令流中调度第一类型（503）的第一指令和第二类型（506）的第二指令的执行顺序。 调度单元包括记录对应于第二指令（503）的地址分量标识符的表。 地址比较器耦合到表。 地址比较器将对应于第一指令的地址组件标识符与表上的地址组件标识符进行比较（504）。 当地址分量标识符与表（506）上的地址分量标识符不同时，调度单元调度在第二指令之前执行的第一指令。

公开(公告)号：WO1986001304A1

公开(公告)日：1986-02-27

申请号：PCT/GB1985000362

申请日：1985-08-14

Applicant: CANADIAN INDUSTRIAL INNOVATION CENTRE/WATERLOO ,  IDEA CORPORATION ,  ASQUITH, Anthony

Inventor： CANADIAN INDUSTRIAL INNOVATION CENTRE/WATERLOO ,  IDEA CORPORATION ,  ASQUITH, Anthony ,  LIT, John, W., Y. ,  HEWAK, Daniel, W.

IPC: G02B06/12

CPC classification number: G02B6/1245 ,  G02B2006/12164

Abstract: A thin-film waveguide lens and a wavelength division multiplexer/demultiplexer (1) embodying such lens. The thin film waveguide lens comprises a thin-film waveguide with end planes essentially normal to the lens axis. A plano-convex overlay layer integral with the waveguide extends the length of the waveguide along the axis, its profile being selected so as to produce a graded effective refractive index in the lens in order to collimate focussed rays and focus collimated rays entering at one end plane for substantially collimated or focussed arrival at the other end plane. The multiplexer/demultiplexer (1) comprises the above thin-film waveguide lens, with one of the end planes constituting an entrance/exit plane (A A') for receiving optical fibres (F1, F2, F3) in an abutting connection, and the other end plane (B B') bearing a diffraction/reflection grating (5). In accordance with the preferred embodiments, the shape of the plano-convex overlay layer is such as to provide an effective index of refraction profile in the waveguide according to the formula n = n0sech(gr), where n is the effective refractive index at the distance r from the axis of the waveguide, n0 is the effective refractive index at the waveguide axis, and g is a constant equal to pi /2f, where is the focal length of the lens, being essentially the distance between end planes.

Abstract translation: 薄膜波导透镜和体现这种透镜的波分复用器/解复用器（1）。 薄膜波导透镜包括具有基本上垂直于透镜轴线的端面的薄膜波导。 与波导成一体的平凸叠层将波导的长度沿着轴线延伸，其轮廓被选择以便在透镜中产生渐变的有效折射率，以便准直聚焦的光线并聚焦在一端进入的准直光线 平面基本准直或聚焦到另一端面。 多路复用器/解复用器（1）包括上述薄膜波导透镜，其中一个端面构成用于在邻接连接中接收光纤（F1，F2，F3）的入射/出射面（A A'），以及 具有衍射/反射光栅（5）的另一端面（B B'）。 根据优选实施例，平凸叠层的形状是根据公式n = n0sech（gr）在波导中提供有效的折射率折射率，其中n是在 距波导轴的距离r，n0是波导轴上的有效折射率，g是等于pi / 2f的常数，其中是透镜的焦距，基本上是端面之间的距离。

公开(公告)号：WO1998021712A2

公开(公告)日：1998-05-22

申请号：PCT/US1997020610

申请日：1997-11-12

Applicant: IDEA CORPORATION

Inventor： IDEA CORPORATION ,  YAMADA, Koichi ,  HAMMOND, Gary, Neil

IPC: G11B00/00

CPC classification number: G06F12/1036 ,  G06F2212/681

Abstract: A method and an apparatus for translating a virtual address into a physical address in a multiple region virtual memory environment. In one embodiment, a translation lookside buffer (TLB) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.

Abstract translation: 一种在多区域虚拟存储器环境中将虚拟地址转换为物理地址的方法和装置。 在一个实施例中，翻译后端缓冲器（TLB）被配置为提供页表条目以建立物理地址。 TLB补充有虚拟散列页表（VHPT），以在出现TLB未命中时提供TLB条目。 替代软件替换方案可以在每个区域的基础上使用，而不是使用与所公开的虚拟地址空间的每个特定区域相关联的专用位的VHPT的默认页面表。 仅当特定区域的特定位和主使能位都被使能时才执行VHPT步行。 否则，执行替代软件替换例程以在TLB未命中的发生中提供TLB替换。

公开(公告)号：WO1998025196A3

公开(公告)日：1998-06-11

申请号：PCT/US1997020506

申请日：1997-11-12

Applicant: IDEA CORPORATION

Inventor： IDEA CORPORATION ,  YEH, Tse-Yu ,  POPLINGHER, Mircea ,  CHEN, Wenliang ,  MULDER, Hans

IPC: G06F09/38

公开(公告)号：WO1998014866A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017369

申请日：1997-09-26

Applicant: IDEA CORPORATION

Inventor： IDEA CORPORATION ,  MORRIS, Dale, C. ,  MILLS, Jack, D.

IPC: G06F09/312

CPC classification number: G06F9/3842 ,  G06F9/30072

Abstract: The present invention provides a method and apparatus for restoring a predicate register set. One embodiment of the invention includes decoding a first instruction ("Instruction set") which specifies a restoring operation to be performed on a predicate register set. In response to the the first instruction, a mask is used to select a plurality of predicate registers that are to be restored ("Mask"). The mask of the present invention consists of a first set of bits, with each bit of the first set of bits corresponding to a register in the predicate register set. When a bit of the first set of bits is set to one, the predicate register corresponding to that bit is restored. In one embodiment, the mask further includes one bit corresponding to a plurality of registers in the predicate register set, wherein when that bit is set to one, the plurality of registers corresponding to that bit are restored ("Restore Unit").

Abstract translation: 本发明提供一种用于恢复谓词寄存器组的方法和装置。 本发明的一个实施例包括解码指定要在谓词寄存器集上执行的恢复操作的第一指令（“指令集”）。 响应于第一条指令，使用掩码来选择要恢复的多个谓词寄存器（“掩码”）。 本发明的掩模由第一组位组成，其中第一组位的每个位对应于谓词寄存器组中的寄存器。 当第一组位的位被设置为1时，对应于该位的谓词寄存器被恢复。 在一个实施例中，掩码还包括对应于谓词寄存器组中的多个寄存器的一个位，其中当该位被设置为1时，与该位对应的多个寄存器被恢复（“恢复单元”）。

公开(公告)号：WO1998008160A1

公开(公告)日：1998-02-26

申请号：PCT/US1997012411

申请日：1997-07-16

Applicant: IDEA CORPORATION

Inventor： IDEA CORPORATION ,  CHANG, Po-Hua

IPC: G06F09/00

CPC classification number: G06F8/447 ,  G06F8/4451 ,  G06F9/30072 ,  G06F9/3848

Abstract: A method and apparatus for handling branch instructions contained within a source program includes applying a set of heuristics to classify each of the branch instructions in the source program as either a hard-to-predict type or a simple type of branch. A system implements a multi-heuristic branch predictor (21) comprising a large, relatively simple branch predictor (23) having many entries, to accommodate the majority of branch instructions encountered in a program, and a second, relatively small, sophisticated branch predictor (24) having a few entries. The sophisticated branch predictor (24) predicts the target addresses of the hard-to-predict branches. By mapping hard-to-predict branches to the sophisticated branch predictor (24), and easy-to-predict branches to the relatively simple branch predictor (23), overall performance is enhanced.

Abstract translation: 用于处理包含在源程序中的分支指令的方法和装置包括应用一组启发式来将源程序中的每个分支指令分类为难以预测的类型或简单类型的分支。 系统实现多启发式分支预测器（21），其包括具有许多条目的大的相对简单的分支预测器（23），以适应在程序中遇到的大多数分支指令，以及第二相对小的复杂分支预测器 24）有几个条目。 复杂的分支预测器（24）预测难以预测的分支的目标地址。 通过将难以预测的分支映射到复杂的分支预测器（24），并且易于预测的分支到相对简单的分支预测器（23），整体性能得到提高。

公开(公告)号：WO1998003908A1

公开(公告)日：1998-01-29

申请号：PCT/US1997011807

申请日：1997-07-07

Applicant: IDEA CORPORATION

Inventor： IDEA CORPORATION ,  YEH, Tsu-Yu ,  POPLINGHER, Mircea ,  FIELDEN, Kent, G. ,  MULDER, Hans ,  GUPTA, Rajiv ,  MORRIS, Dale ,  SCHLANSKER, Michael

IPC: G06F09/00

CPC classification number: G06F9/3804 ,  G06F9/3836 ,  G06F9/3846

Abstract: A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, which also specifies a target address of the branch. A block of target instructions (18), starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of the limited memory bandwith.

Abstract translation: 在程序指令序列的执行中减少指令提取损失的处理器和方法包括在分支之前的位置处插入到程序中的分支预测指令。 分支预测指令具有指定可能被采用或不被采用的分支的操作​​码，其也指定分支的目标地址。 从目标地址开始的目标指令（18）的块被预取到处理器的指令高速缓存中，使得指令在程序中遇到分支的点之前可用于执行。 操作码还指定了目标指令块的大小的指示，以及程序序列中的通向分支预测指令的目标的路径的跟踪向量，以更好地利用有限的存储带宽。

公开(公告)号：WO1998000769A2

公开(公告)日：1998-01-08

申请号：PCT/US1997011297

申请日：1997-06-25

Applicant: IDEA CORPORATION

Inventor： IDEA CORPORATION ,  KENNER, H., Roland ,  KARP, Alan ,  CHEN, William

IPC: G06F00/00

CPC classification number: G06F9/3865 ,  G06F8/433 ,  G06F8/445 ,  G06F9/3834 ,  G06F9/3838

Abstract: According to one aspect of the invention, a machine-readable medium having stored thereon data representing sequences of instructions is described. When executed by a computer system, the sequences of instructions cause the computer system to perform a series of steps. One of these steps involves preloading one of a set of registers data retrieved from a memory starting at a first address. Another of these steps involves storing memory conflict information representing the first address. This memory conflict information is later used for determining if a memory conflict has occurred. Another of these steps involves storing data at a second address in the memory. Yet another of these steps involves determining if a memory conflict has occurred between the first address and the second address using the previously stored memory conflict information. If a memory conflict occurred between the first and second addresses, then one of the registers is reloaded with the data located at the first address. However, if a memory conflict did not occur between the first and second addresses, then the memory conflict information is left for use during subsequent memory conflict checks. According to one embodiment of the invention, the data is reloaded into a register by causing the computer system to branch to recovery code. According to another embodiment of the invention, the data is reloaded into a register without performing any branch instructions.

Abstract translation: 根据本发明的一个方面，描述了存储有表示指令序列的数据的机器可读介质。 当由计算机系统执行时，指令序列使计算机系统执行一系列步骤。 这些步骤之一涉及预先加载从第一地址开始的从存储器检索的一组寄存器数据中的一个。 这些步骤中的另一个涉及存储表示第一地址的存储器冲突信息。 该存储器冲突信息稍后用于确定是否发生内存冲突。 这些步骤中的另一个涉及将数据存储在存储器中的第二地址处。 这些步骤中的另一个涉及使用先前存储的存储器冲突信息确定在第一地址和第二地址之间是否发生存储器冲突。 如果在第一和第二地址之间发生存储器冲突，则其中一个寄存器被重新加载位于第一个地址的数据。 但是，如果在第一个和第二个地址之间没有发生内存冲突，那么在随后的内存冲突检查期间，剩余的内存冲突信息将被使用。 根据本发明的一个实施例，通过使计算机系统分支到恢复码，将数据重新加载到寄存器中。 根据本发明的另一实施例，将数据重新加载到寄存器中，而不执行任何分支指令。

公开(公告)号：US20200298099A1

公开(公告)日：2020-09-24

申请号：US16649251

申请日：2018-09-20

Applicant: AT idea Corporation

Inventor： Akihiko TANAKA

IPC: A63F7/04

Abstract: A piece of three-dimensional maze, wherein at least two of six faces of a cube have opening faces such that a path connecting the opening faces of two faces is defined by flat plate of the cube.

公开(公告)号：EP1023660B1

公开(公告)日：2005-12-28

申请号：EP98952211.5

申请日：1998-10-08

Applicant: Idea Corporation

Inventor： HULL, James, M. ,  FIELDEN, Kent ,  MULDER, Hans ,  SHARANGPANI, Harshvardhan

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3853

Abstract: A processor having a large register file (10) utilizes a template field for encoding a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of the processor are similarly categorized into different types, wherein each instruction type may be executed on one or more of the execution unit types. The instructions are grouped together into 128-bit sized and aligned containers called bundles, with each bundle includes a plurality of instruction slots and a template field that specifies the mapping of the instruction slots to the execution unit types.