公开(公告)号：WO1998021712A2

公开(公告)日：1998-05-22

申请号：PCT/US1997020610

申请日：1997-11-12

Applicant: IDEA CORPORATION

Inventor： IDEA CORPORATION ,  YAMADA, Koichi ,  HAMMOND, Gary, Neil

IPC: G11B00/00

CPC classification number: G06F12/1036 ,  G06F2212/681

Abstract: A method and an apparatus for translating a virtual address into a physical address in a multiple region virtual memory environment. In one embodiment, a translation lookside buffer (TLB) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.

Abstract translation: 一种在多区域虚拟存储器环境中将虚拟地址转换为物理地址的方法和装置。 在一个实施例中，翻译后端缓冲器（TLB）被配置为提供页表条目以建立物理地址。 TLB补充有虚拟散列页表（VHPT），以在出现TLB未命中时提供TLB条目。 替代软件替换方案可以在每个区域的基础上使用，而不是使用与所公开的虚拟地址空间的每个特定区域相关联的专用位的VHPT的默认页面表。 仅当特定区域的特定位和主使能位都被使能时才执行VHPT步行。 否则，执行替代软件替换例程以在TLB未命中的发生中提供TLB替换。

公开(公告)号：EP1027656B1

公开(公告)日：2003-05-02

申请号：EP97946926.9

申请日：1997-11-12

Applicant: Idea Corporation

Inventor： YAMADA, Koichi ,  HAMMOND, Gary, Neil

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F2212/681

Abstract: A method and an apparatus for translating a virtual address into a physical address in a multiple region virtual memory environment. In one embodiment, a translation lookside buffer (TLB) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.

公开(公告)号：EP1027656A2

公开(公告)日：2000-08-16

申请号：EP97946926.9

申请日：1997-11-12

Applicant: Idea Corporation

Inventor： YAMADA, Koichi ,  HAMMOND, Gary, Neil

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F2212/681

Abstract: A method and an apparatus for translating a virtual address (305) into a physical address (315) in a multiple region virtual memory environment. In one embodiment, a translation lookside buffer (TLB) (313) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) (325) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit (311) associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit (319) are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.

公开(公告)号：EP0976048A1

公开(公告)日：2000-02-02

申请号：EP98906108.0

申请日：1998-02-04

Applicant: Idea Corporation

Inventor： YAMADA, Koichi ,  HAMMOND, Gary, N. ,  HAYS, Jim ,  ROSS, Jonathan, Kent ,  BURGER, Stephen ,  BRYG, William, R.

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F2212/652

Abstract: A page table walker (305) uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. A page size storage area (315) is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker (305) includes a selection unit (320) coupled to the page size storage area (315), as well as a page entry address generator (325) coupled to the selection unit (320). For each of the virtual addresses received, the selection unit (320) positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator (325) identifies an entry in a page table (310) based on those bits.