公开(公告)号：US20150357191A1

公开(公告)日：2015-12-10

申请号：US14760890

申请日：2013-01-17

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCE

Inventor： Dongmei Li ,  Xin Chen ,  Shengfa Liang ,  Jiebin Niu ,  Peiwen Zhang ,  Yu Liu ,  Xiaojing Li ,  Shuang Zhan ,  Hao Zhang ,  Qing Luo ,  Changqing Xie ,  Ming Liu

IPC: H01L21/02 ,  H01L21/465

CPC classification number: H01L21/02565 ,  B82Y10/00 ,  B82Y40/00 ,  G01N33/004 ,  G01N33/005 ,  H01L21/02422 ,  H01L21/02581 ,  H01L21/02603 ,  H01L21/02614 ,  H01L21/465 ,  Y02A50/243

Abstract: The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of H2PtCl6 so as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt. The present invention is simple and practical and the sensitivity and reliability of the doped sensor on the gas of CO and H2 are greatly improved.

Abstract translation: 本公开提供了一种用于制造原位掺杂有Pt的NiO的有序纳米线阵列的方法，包括：在耐高温和绝缘的衬底上生长Ni层; 在Ni层上施加光致抗蚀剂，通过在光致抗蚀剂上施加电子束蚀刻来图案化有序纳米线阵列的图案区域，在有序纳米线阵列的图案区域上生长Ni，用丙酮剥离光致抗蚀剂并蚀刻 Ni层，以便蚀刻生长在衬底表面上的Ni层，并将Ni留在有序纳米线阵列的图案区上以形成有序的Ni纳米线阵列; 将有序的Ni纳米线阵列浸入H2PtCl6溶液中，通过置换反应置换Ni纳米线阵列上的Pt; 并在氧化炉中氧化附着有Pt的Ni纳米线阵列，以获得掺杂有Pt的NiO的有序纳米线阵列。 本发明简单实用，掺杂传感器对CO和H2气体的灵敏度和可靠性大大提高。

公开(公告)号：US20150318354A1

公开(公告)日：2015-11-05

申请号：US14646583

申请日：2013-08-12

Applicant: INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCE

Inventor： Huaxiang Yin ,  Huilong Zhu ,  Xiaolong Ma

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/1054 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

Abstract translation: 半导体器件包括沿着第一方向在衬底上延伸的翅片; 沿着第二方向延伸穿过翅片的门; 和源极/漏极区域和在栅极的相对侧的鳍上的栅极间隔物，其中在鳍的顶部和/或侧壁上存在表面层。

公开(公告)号：US10192963B2

公开(公告)日：2019-01-29

申请号：US15539597

申请日：2015-07-16

Applicant: Institute Of Microelectronics, Chinese Academy of Science

Inventor： Shengkai Wang ,  Honggang Liu ,  Bing Sun ,  Hudong Chang

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/20 ,  H01L29/51 ,  H01L21/285 ,  H01L29/423

Abstract: The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlxY2-xO3 interface passivation layer formed on the group III-V substrate; and a high dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2≤x≤1.9. The composite gate dielectric layer modifies the Al/Y ratio of the AlxY2-xO3 interface passivation layer, changes the average number of atomic coordination in the AlxY2-xO3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlxY2-xO3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improves tolerance of the dielectric layer on the voltage, and improves the quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.