公开(公告)号：WO2008106369A2

公开(公告)日：2008-09-04

申请号：PCT/US2008/054689

申请日：2008-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BUCK, Nathan, C. ,  DUBUQUE, John, P. ,  FOREMAN, Eric, A. ,  HABITZ, Peter, A. ,  KALAFALA, Kerim ,  QI, Peihua ,  VISWESWARIAH, Chandramouli ,  WANG, Xiaoyue

Inventor： BUCK, Nathan, C. ,  DUBUQUE, John, P. ,  FOREMAN, Eric, A. ,  HABITZ, Peter, A. ,  KALAFALA, Kerim ,  QI, Peihua ,  VISWESWARIAH, Chandramouli ,  WANG, Xiaoyue

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path (20, 30, 50) leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path (20, 30, 50) based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

Abstract translation: 公开了用于分析集成电路的时序设计的方法，系统和计算机程序产品。 根据实施例，用于分析集成电路的定时设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析，选择静态定时测试点的静态定时测试; 选择导致静态定时测试的静态定时测试点的定时路径（20,30,50）; 基于至少一个统计学独立参数的联合概率分布来确定所述定时路径（20,30,50）的综合松弛路径可变性; 并基于综合的松弛路径变异性分析时序设计。

公开(公告)号：WO2008106369A3

公开(公告)日：2008-10-16

申请号：PCT/US2008054689

申请日：2008-02-22

Applicant: IBM ,  BUCK NATHAN C ,  DUBUQUE JOHN P ,  FOREMAN ERIC A ,  HABITZ PETER A ,  KALAFALA KERIM ,  QI PEIHUA ,  VISWESWARIAH CHANDRAMOULI ,  WANG XIAOYUE

Inventor： BUCK NATHAN C ,  DUBUQUE JOHN P ,  FOREMAN ERIC A ,  HABITZ PETER A ,  KALAFALA KERIM ,  QI PEIHUA ,  VISWESWARIAH CHANDRAMOULI ,  WANG XIAOYUE

IPC: G06F9/45

CPC classification number: G06F17/5031

Abstract: Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path (20, 30, 50) leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path (20, 30, 50) based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

Abstract translation: 公开了用于分析集成电路的时序设计的方法，系统和计算机程序产品。 根据一个实施例，一种用于分析集成电路的时序设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析选择关于静态时序测试点的静态时序测试; 选择通向所述静态时序测试点的时序路径（20,30,50）用于所述静态时序测试; 基于至少一个统计独立参数的联合概率分布确定所述定时路径（20,30,50）的综合松弛路径可变性; 并根据综合松弛路径变化分析时间设计。