公开(公告)号：WO2008106369A3

公开(公告)日：2008-10-16

申请号：PCT/US2008054689

申请日：2008-02-22

Applicant: IBM ,  BUCK NATHAN C ,  DUBUQUE JOHN P ,  FOREMAN ERIC A ,  HABITZ PETER A ,  KALAFALA KERIM ,  QI PEIHUA ,  VISWESWARIAH CHANDRAMOULI ,  WANG XIAOYUE

Inventor： BUCK NATHAN C ,  DUBUQUE JOHN P ,  FOREMAN ERIC A ,  HABITZ PETER A ,  KALAFALA KERIM ,  QI PEIHUA ,  VISWESWARIAH CHANDRAMOULI ,  WANG XIAOYUE

IPC: G06F9/45

CPC classification number: G06F17/5031

Abstract: Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path (20, 30, 50) leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path (20, 30, 50) based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

Abstract translation: 公开了用于分析集成电路的时序设计的方法，系统和计算机程序产品。 根据一个实施例，一种用于分析集成电路的时序设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析选择关于静态时序测试点的静态时序测试; 选择通向所述静态时序测试点的时序路径（20,30,50）用于所述静态时序测试; 基于至少一个统计独立参数的联合概率分布确定所述定时路径（20,30,50）的综合松弛路径可变性; 并根据综合松弛路径变化分析时间设计。

公开(公告)号：WO2007068690A1

公开(公告)日：2007-06-21

申请号：PCT/EP2006/069589

申请日：2006-12-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  ZOLOTOV, Vladimir ,  VISWESWARIAH, Chandramouli ,  VENTKATESWARAN, Natesan ,  XIONG, Jinjun

Inventor： ZOLOTOV, Vladimir ,  VISWESWARIAH, Chandramouli ,  VENTKATESWARAN, Natesan ,  XIONG, Jinjun

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/84

Abstract: A method for determining criticality probability of an edge of a timing graph of a circuit is described. The method includes forming a directed acyclic timing graph corresponding to a circuit being timed, performing statistical timing of the circuit, for each edge of interest, defining a cutset that divides the timing graph into a plurality of parts, determining an edge slack for each edge in the cutset, computing a statistical maximum of all edge slacks in the cutset, and inferring edge criticality probabilities of each edge from the statistical maximum. A system for determining criticality probability of an edge of a timing graph of a circuit is also described.

Abstract translation: 描述了用于确定电路的时序图的边缘的临界概率的方法。 该方法包括形成对应于正在定时的电路的有向非循环时序图，对于感兴趣的每个边缘执行电路的统计定时，定义将定时图分成多个部分的切片，确定每个边缘的边缘松弛 在切片中，计算切片中所有边缘松弛的统计最大值，并从统计最大值推断每个边缘的边缘关键概率。 还描述了用于确定电路的时序图的边缘的关键概率的系统。

公开(公告)号：WO2008134215A1

公开(公告)日：2008-11-06

申请号：PCT/US2008/059826

申请日：2008-04-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FOREMAN, Eric, A. ,  GRISE, Gary, D. ,  HABITZ, Peter, A. ,  IYENGAR, Vikram ,  LACKEY, David, E. ,  VISWESWARIAH, Chandramouli ,  XIONG, Jinjun ,  ZOLOTOV, Vladimir

Inventor： FOREMAN, Eric, A. ,  GRISE, Gary, D. ,  HABITZ, Peter, A. ,  IYENGAR, Vikram ,  LACKEY, David, E. ,  VISWESWARIAH, Chandramouli ,  XIONG, Jinjun ,  ZOLOTOV, Vladimir

IPC: G11B27/00

CPC classification number: G06F17/5031 ,  G06F2217/10

Abstract: Methods, systems and program products for evaluating an IC chip (130, 200) are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design (132); creating at-functional-speed test (AFST) robust paths (156) for an IC chip (130, 200), the created robust paths (156) representing a non-comprehensive list of AFST robust paths (156) for the IC chip (130, 200); and re-running the SSTA with the SSTA delay model setup (152) based on the created robust paths (156). A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip (130, 200) is evaluated based on the process coverage.

Abstract translation: 公开了用于评估IC芯片（130,200）的方法，系统和程序产品。 在一个实施例中，该方法包括运行全IC芯片设计（132）的统计静态时序分析（SSTA）; 创建用于IC芯片（130,200）的功能速度测试（AFST）鲁棒路径（156），所创建的鲁棒路径（156）表示用于IC芯片的AFST鲁棒路径（156）的非全面列表 130,200）; 并且基于所创建的鲁棒路径（156），通过SSTA延迟模型设置（152）重新运行SSTA。 计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定IC芯片（130,200）。

公开(公告)号：WO2008106369A2

公开(公告)日：2008-09-04

申请号：PCT/US2008/054689

申请日：2008-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BUCK, Nathan, C. ,  DUBUQUE, John, P. ,  FOREMAN, Eric, A. ,  HABITZ, Peter, A. ,  KALAFALA, Kerim ,  QI, Peihua ,  VISWESWARIAH, Chandramouli ,  WANG, Xiaoyue

Inventor： BUCK, Nathan, C. ,  DUBUQUE, John, P. ,  FOREMAN, Eric, A. ,  HABITZ, Peter, A. ,  KALAFALA, Kerim ,  QI, Peihua ,  VISWESWARIAH, Chandramouli ,  WANG, Xiaoyue

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path (20, 30, 50) leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path (20, 30, 50) based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

Abstract translation: 公开了用于分析集成电路的时序设计的方法，系统和计算机程序产品。 根据实施例，用于分析集成电路的定时设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析，选择静态定时测试点的静态定时测试; 选择导致静态定时测试的静态定时测试点的定时路径（20,30,50）; 基于至少一个统计学独立参数的联合概率分布来确定所述定时路径（20,30,50）的综合松弛路径可变性; 并基于综合的松弛路径变异性分析时序设计。